WDT times not as expected 18f46k80

[longpole001]

hi guys i am trying to find why the WDT timeout is not as i am expecting

as i understand it the WDT sends a 4ms pulse originated from the 31Khz osc to the post scaler and gives 4ms x postscaller when the sleep is set

i have set it up for 4ms x 16384 = 65.53 sec , but its triggering at @ 93sec

wondering what may be the problem as i am sure the osc is set correctly to use the LF-INTOSLFO

;----- CONFIG1L Options --------------------------------------------------
    CONFIG XINST     = OFF 
    CONFIG SOSCSEL   = DIG        ; Digital (SCLKI) mode; I/O port functionality of RC0 and RC1 is enabled
    CONFIG INTOSCSEL = LOW        ; LF-INTOSC in low-power mode during Sleep
    CONFIG RETEN     = ON         ; Ultra Low power regulator is Enabled  (Controlled by SRETEN bit)when in sleep  WDTCON.4)

;----- CONFIG1H Options --------------------------------------------------
    CONFIG IESO      = OFF 
    CONFIG FCMEN     = OFF
    CONFIG PLLCFG    = OFF 
    CONFIG FOSC      = INTIO2     ; Internal RC oscillator  , PORTA.6 , PORTA.7 as I/O
 
;----- CONFIG2L Options --------------------------------------------------
    CONFIG BORPWR    = ZPBORMV    ; ZPBORMV instead of BORMV is selected
    CONFIG BORV      = 2          ; 2V
    CONFIG BOREN     = SBORDIS    ; Enabled in hardware, SBOREN disabled
    CONFIG PWRTEN    = OFF 

;----- CONFIG2H Options --------------------------------------------------
    CONFIG  WDTPS    = 16384       ; 1:32768  = 4ms x 32768 =  aprox 139 sec for watchdog timeout 
    CONFIG  WDTEN    = SWDTDIS    ; WDT enabled in hardware; SWDTEN bit disabled
  
;----- CONFIG3L Options --------------------------------------------------
; no register in the device 

;----- CONFIG3H Options --------------------------------------------------
    CONFIG MCLRE     = ON         ; MCLR ENabled FOR DIAG , RG5 DISabled
    CONFIG MSSPMSK   = MSK7       ; 7 Bit address masking mode
    CONFIG CANMX     = PORTB      ; ECAN TX and RX pins are located on RB2 and RB3, respectively

;----- CONFIG4L Options --------------------------------------------------
    CONFIG BBSIZ     = BB1K       ; 1K word Boot Block size
    CONFIG STVREN    = ON 

;----- CONFIG5L Options --------------------------------------------------  
    
    CONFIG CP0       = ON         ;  MEMORY BLOCK 0 CODE PROTECT BIT - 7KW 800h  - 3FFFh ( when 1K BOOT OPTION used )
    CONFIG CP1       = ON         ;  MEMORY BLOCK 1 CODE PROTECT BIT - 8KW 4000h - 7FFFh
    CONFIG CP2       = ON         ;  MEMORY BLOCK 2 CODE PROTECT BIT - 8KW 8000h - BFFFh
    CONFIG CP3       = ON         ;  MEMORY BLOCK 3 CODE PROTECT BIT - 8KW C000h - FFFFh
   
   
;----- CONFIG5H Options --------------------------------------------------  
   CONFIG  CPD       = OFF        ; EEPROM DATA PREOTECT BIT - EXTERNAL R/W
   CONFIG  CPB       = ON         ; BOOT BLOCK CODE PROTECT BIT 

;----- CONFIG6L Options --------------------------------------------------  
    CONFIG WRT0      = OFF        ; MEMORY BLOCK WRITE PROTECT BIT 
    CONFIG WRT1      = OFF
    CONFIG WRT2      = OFF 
    CONFIG WRT3      = OFF
  
  
;----- CONFIG6H Options --------------------------------------------------  
    CONFIG WRTD      = OFF       ; EEPROM WRITE PROTECT BIT - INTERNAL AND EXTERNAL 
    CONFIG WRTB      = ON        ; BOOT BLOCK WRITE PROTECT 
    CONFIG WRTC      = ON        ; CONFIGURATION REGISTER WRITE PROTECT BIT 
 
;----- CONFIG7L Options --------------------------------------------------  
     CONFIG EBTR0     = OFF      ; MEMORY READ TABLE BLOCK PROTECT 
     CONFIG EBTR1     = OFF
     CONFIG EBTR2     = OFF
     CONFIG EBTR3     = OFF
    
;----- CONFIG7H Options --------------------------------------------------  
    CONFIG EBTRB     = OFF      ; TABLE READ PROTECT BOOT

 '----------- 18F46K80  - PIC chip Dephalt settings --------------------
 
 
   OSCCON   = %00110000     ' Select 1Mhz - using 1Mhz internal with PPLx4 in Config1H<3:0>  =  IDLEN =0 , 8Mhz , OSTS=0,RFIOFS=1,RC_Run (1x) OSC using PLL  
                            ' Bit 7 IDLEN =0 ( sleep mode when sleep instraction executed)
                            ' Bits 6-4 -  111 = 16Mhz , 110 = 8MHz ,101 = 4 MHz, 100 = 2MHz 011 = 1MHz
                            ' If INTTSRC=0 and MFIOSEL= 0 then 010 = HF-INTOSC/32 (500Khz), 001 = HF-INTOSC/64 (250Khz) ,000 = LF-INTOSC     (31.25Khz)
                            ' If INTTSRC=0 and MFIOSEL= 1 then 010 = MF-INTOSC    (500Khz), 001 = MF-INTOSC/2  (250Khz) ,000 = LF-INTOSC     (31.25Khz)
                            ' If INTTSRC=1 and MFIOSEL= 0 then 010 = HF-INTOSC/32 (500Khz), 001 = HF-INTOSC/64 (250Khz) ,000 = HF-INTOSC/512 (31.25Khz)
                            ' If INTTSRC=1 and MFIOSEL= 1 then 010 = MF-INTOSC    (500Khz), 001 = MF-INTOSC/2  (250Khz) ,000 = MF-INTOSC/16  (31.25Khz)
                            ' Note: INTSRC = OSCTUNE<7> and MFIOSEL = OSCCON2<0>
                            ' Bit 3 - OSTS = 0 - Osc startup time out  is ruinning from internal OSC ( HF, MF or -INTOSLFC) 
                            ' Bit 2 - HFIOFS =1 ( INTOSC Frq stable bit  -  1 = stable , 0 = not stable 
                            ' Bits 1-0 - 00= Dephalt Pri OSc ( OSC1/2 or HF-INTOSC with/without PLL set in FOSC,3:0> config1H <3.0>
                            '            01 = SOSC osc
                            '            1x = Internal osc ( LF, MF,HF-INTOSC)  
   
  ' OSCCON2 = $00            ' Bit 7 n/a , Bit 6 - SOSCRUN - Run status bit , Bit 5-4 n/a, 
                            ' Bit 3 = SOASCGO - Osc Start control bit 1 = OSC running , 0 = OSC shut off if no requests for it 
                            ' Bit 2 n/a , Bit 1 - MFIOFS 1= MFINTOSC stable  0 = Not stable 
                            ' Bit 0 MFIOSEL - 1 = MF-INTOSC replaces HF-ISTOSC Freq for 500Khz,250Khz,31.25KHz) 0 = MF-INTOSC not used 
  
   OSCTUNE = %00000000      ' Bit 7  - INTSRC - internal LF Source Select 1 = 31.25 from 16Mhz Internal /512 HF-INTOSC ) 0 = Internal 31khz OSC 
                            ' Bit 6 - PLLEN - 1 PLL enabled  , 0 = PLL disabled 
                            ' Bits 5-0 Frequancy callibaration 00000 = centre Frq
                            
   WDTCON = %00010000       ' use ultra low power mode when in sleep - disable  regulator in sleep mode  
                            ' Bit7 = REGSLP- Regulator Voltage Sleep Enable - 1= Reg goes into low-power Mode when in sleep mode ,0 = Reg stay in normal mode 
                            ' Bit6= n/a , Bit5 = ULPLVL - Ultra lowpower Wakeup output sel 1= Vout on RA0 0= Vout on RA1 ( no effect if WDTEN in config is set  )
                            ' Bit4= SRETEN = Regulator Volt Sleep Disable bit - 1= goes into Ultra lOwpower mode in sleep ( CONFIG1L.0 =0 MUST BE SET) 
                            ' Bit3=n/a , Bit2 = ULPEN - Ultra Low Power Wakup Module enable 1 = enabled , 0 = disabled 
                            ' Bit1=ULPSINK- Ultra Low-power Wakeup Current Sink Enable  1= Sink enabled 0 = Sink disabled ( Not valid if ULPEN=0 ) 
                            ' Bit0= SWDTEN -Watchdog Timer Enable  = 1= enable watchdog 0 = Disable Watchdog ( no effect if WDTEN in config is set  )

[longpole001]

I would like to change the WDT value in CONFIG2h while in the program
is this possible , and how is it done ?

[pedja089]

It is possible.
DT done that, and post code example.
Here is link to topic
http://www.picbasic.co.uk/forum/showthread.php?t=4093
But link's are dead. And I can't find it anywhere on my pc...
As you can see from Darrel's post, you need just to copy PBP's WRITE command and set CFGS bit.

EDIT:
Here it is
http://www.picbasic.co.uk/forum/atta...8&d=1420287592

[longpole001]

ok thanks ill see if i can get it work

i would like to change it to about 4 different setting depending on the functions triggering the sleep

[longpole001]

wow that made it simple , and DT did this bak in 2006 very cool

thanks pedja089

[pedja089]

Glad to help

[HenrikOlsson]

How often are you going to sleep and how often do you expect it to actually change?
Remember that the CONFIG words are in flash memory. If you're changing those bits often enough you're going to wear them out.
Datasheet claims 10000 cycles typical, if you're writing once per hour you're hitting 10000 writes after 14 months in operation. If you're writing once per second then, well then it's 3 hours....

/Henrik.

[longpole001]

THATS A GOOD POINT - thanks hendrick i never considered that issue

and that will be an issue in the long run for any type of writes to flash

it would be good to make the config words read a location in the EErpom , which would not be a problem for change updates

now is that possible ???

[longpole001]

for this app the changes are not that often , but wearing out the flash due to constant changes is a concern ,

i have 4 sleep types at the moment with only 2 times settings for the WDT , and they change based on options selected and should not change that often after setup , but the ability to change them is a good one

one approch was to apply multi sleep settings of the base time period of the WDT , so if option needed 512x 4ms , but option 2 need 2048 x 4ms then just ensure you put the unit back to sleep x 4 when that option2 is required

[richard]

if you need variable wdt reset times why not have the wdt reset decrement a counter and go back to sleep , and only fully wake when counter = 0 , that way wdt reset is infinitely variable with no flash writes at all

[rmteo]

....i have 4 sleep types at the moment with only 2 times settings for the WDT , and they change based on options selected and should not change that often after setup , but the ability to change them is a good one

Sounds like you are wanting to deal with asynchronous events. If that is the case, then the "EXIt BY INTERRUPT" feature should be used.

3.5.1 EXIT BY INTERRUPT

Any of the available interrupt sources can cause the
device to exit from an Idle mode or the Sleep mode to
a Run mode. To enable this functionality, an interrupt
source must be enabled by setting its enable bit in one
of the INTCON or PIE registers. The exit sequence is
initiated when the corresponding interrupt flag bit is set.

The instruction immediately following the SLEEP
instruction is executed on all exits by interrupt from Idle
or Sleep modes. Code execution then branches to the
interrupt vector if the GIE/GIEH bit of the INTCON
register is set, otherwise code execution continues
without branching.

[longpole001]

i have the other sleep interupts going to thier routines ok
WDT has now been set to my required min time
and a WDT counter decriment the counter with pick off points as required
i think its a better way in the long run