you didn't read the whole post of the config fuse setting. I found the issue later on the same thread. If you want to use the new CONFIG directive, you MUST set them in the pic18F4550.inc file. As now PBP don't support the new directive... this where the Config file (stated in the thread) where born
NOW being said... if i use the CONFIG stuff bellow.. in wich i did few error for my own pleasure ..
and i place it in the 18F4550.inc file like thatCode:CONFIG PLLDIV = 5 ; Divide by 5 (20 MHz oscillator input) CONFIG CPUDIV = OSC2_PLL3 ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] CONFIG USBDIV = 1 ; USB clock source comes directly from the primary oscillator block with no postscale CONFIG FOSC = HS ; HS oscillator, HS used by USB CONFIG FCMEM = ON ; Fail-Safe Clock Monitor enabled CONFIG IESO = ON ; Oscillator Switchover mode enabled CONFIG PWRT = ON ; PWRT enabled CONFIG BOR = ON ; Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG BORV = 2 CONFIG VREGEN = ON ; USB voltage regulator enabled CONFIG WDT = ON ; HW Enabled - SW Disabled CONFIG WDTPS = 1 ; 1:1 CONFIG MCLRE = ON ; MCLR pin enabled; RE3 input pin disabled CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation CONFIG PBADEN = ON ; PORTB<4:0> pins are configured as analog input channels on Reset CONFIG CCP2MX = ON ; CCP2 input/output is multiplexed with RC1 CONFIG STVREN = ON ; Stack full/underflow will cause Reset CONFIG LVP = OFF ; Single-Supply ICSP disabled CONFIG ICPRT = OFF ; ICPORT disabled CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) CONFIG DEBUG = OFF ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) not code-protected CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) not code-protected CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected CONFIG CPD = OFF ; Data EEPROM not code-protected CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) not write-protected CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) not write-protected CONFIG WRTB = OFF ; Configuration registers (300000-3000FFh) not write-protected CONFIG WRTC = OFF ; Boot block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ; Data EEPROM not write-protected CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks
if i used the kinda unusefull code bellowCode:;**************************************************************** ;* 18F4550.INC * ;* * ;* By : Leonard Zerman, Jeff Schmoyer * ;* Notice : Copyright (c) 2004 microEngineering Labs, Inc. * ;* All Rights Reserved * ;* Date : 12/31/04 * ;* Version : 2.46 * ;* Notes : * ;**************************************************************** NOLIST ifdef PM_USED LIST "Error: PM does not support this device. Use MPASM." NOLIST else LIST LIST p = 18F4550, r = dec, w = -311, f = inhx32 INCLUDE "P18F4550.INC" ; MPASM Header CONFIG PLLDIV = 5 ; Divide by 5 (20 MHz oscillator input) CONFIG CPUDIV = OSC2_PLL3 ; [OSC1/OSC2 Src: /2][96 MHz PLL Src: /3] CONFIG USBDIV = 1 ; USB clock source comes directly from the primary oscillator block with no postscale CONFIG FOSC = HS ; HS oscillator, HS used by USB CONFIG FCMEM = ON ; Fail-Safe Clock Monitor enabled CONFIG IESO = ON ; Oscillator Switchover mode enabled CONFIG PWRT = ON ; PWRT enabled CONFIG BOR = ON ; Brown-out Reset enabled in hardware only (SBOREN is disabled) CONFIG BORV = 2 CONFIG VREGEN = ON ; USB voltage regulator enabled CONFIG WDT = ON ; HW Enabled - SW Disabled CONFIG WDTPS = 1 ; 1:1 CONFIG MCLRE = ON ; MCLR pin enabled; RE3 input pin disabled CONFIG LPT1OSC = OFF ; Timer1 configured for higher power operation CONFIG PBADEN = ON ; PORTB<4:0> pins are configured as analog input channels on Reset CONFIG CCP2MX = ON ; CCP2 input/output is multiplexed with RC1 CONFIG STVREN = ON ; Stack full/underflow will cause Reset CONFIG LVP = OFF ; Single-Supply ICSP disabled CONFIG ICPRT = OFF ; ICPORT disabled CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode) CONFIG DEBUG = OFF ; Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected CONFIG CP2 = OFF ; Block 2 (004000-005FFFh) not code-protected CONFIG CP3 = OFF ; Block 3 (006000-007FFFh) not code-protected CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected CONFIG CPD = OFF ; Data EEPROM not code-protected CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected CONFIG WRT2 = OFF ; Block 2 (004000-005FFFh) not write-protected CONFIG WRT3 = OFF ; Block 3 (006000-007FFFh) not write-protected CONFIG WRTB = OFF ; Configuration registers (300000-3000FFh) not write-protected CONFIG WRTC = OFF ; Boot block (000000-0007FFh) not write-protected CONFIG WRTD = OFF ; Data EEPROM not write-protected CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks CONFIG EBTR2 = OFF ; Block 2 (004000-005FFFh) not protected from table reads executed in other blocks CONFIG EBTR3 = OFF ; Block 3 (006000-007FFFh) not protected from table reads executed in other blocks CONFIG EBTRB = OFF ; Boot block (000000-0007FFh) not protected from table reads executed in other blocks NOLIST endif LIST EEPROM_START EQU 0F00000h BLOCK_SIZE EQU 32
<img src="http://www.picbasic.co.uk/forum/attachment.php?attachmentid=964&stc=1&d=1152676768 ">
No error, no nothing.. Config fuses? no problem
<img src="http://www.picbasic.co.uk/forum/attachment.php?attachmentid=965&stc=1&d=1152676888 ">
I've heard somewhere that you should change all config fuse to be sure that all will be considered.
Using the OLD method is still working.. read the config fuse thread, there's @ errorlevel stuff... read it 'till the end
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