I’d have thought it’s the internal RC clock that would be the option wanting to be stabilised
Do you have any basis for that or is it just agut feeling? Is it an RC clock? I can't find in the datasheet what kind of osc the internal 4Mhz clock is, perhaps I didn't look hard enough.

Seems to me the internal osc is physically closer, has optimal caps, and a load of other things I can't think of.

Anyway I think your idea of using an RC to hold MCRL for a short while is vcg's only option if he is uncomfortable turning off PWRT (which he has to to achieve 50Ms reliably).

George