RS-232 confusion

[richard]

getting info here is a bit like pulling teeth , but lets assume a 48mhz clock and that timer4 is free along with a pin like portb .2

some vars
bit_is var byte 
I_data var PORTB.2    'lets call this the input

a routine
bit_test:
bit_is =0
t4con=0   ' timer off
tmr4=0   ' clear timer 
pir3.3=0  'clear timer overflow flag

while ( ! i_data) : wend 'wait here till input goes high  to sync up
 while ( i_data) : wend  ' wait here till input goes low
t4con=6     ;  prescale 16 timer on
 while ( ! i_data) : wend  ' wait here till input goes high  
 if  pir3.3 then bit_is=1  ;  offtime > 340 uS  
else
  bit_is=0 '  the offtime < 340 uS 

endif
       
 return

it could be nicer if
1 does the line idle high or low
2 what does a start bit look like
3 how many bits in a session
4 100uS / Off - 400uS a 1 or a 0 ?

[Christopher4187]

If you only want to know ON/OFF duration of 18v signal, why not use the signal to control the base of a transistor that would send 5v to a PIC?

Then I would use interrupts on that pin and use a timer.

I'm a novice when it comes to the timers and interrupts. Seems like a good idea that's worth trying.

1 does the line idle high or low

Idles low.

2 what does a start bit look like

1ms on/1ms off

3 how many bits in a session

100

4 100uS / Off - 400uS a 1 or a 0 ?

It's a 1 but it can vary. Before the packet is received, I will know what is a 0 and what is a 1.

[richard]

this should get close to it

define OSC 48
some vars
bits var byte[13] ' an array to hold the 100 bits
I_data var PORTB.2    'lets call this the input
bit_count var byte
 
 
'a subroutine
bit_read:
t4con=0   ' timer off
tmr4=0   ' clear timer
bit_count = 0
while ( i_data) : wend  ' wait here till input goes idle
while ( ! i_data) : wend 'wait here till input goes high  to sync up
t4con=$7e  '256:1// count of 45 or so = 1mS
while ( i_data) : wend  ' wait here till input goes low
t4con=0   ' timer off
if (tmr4 >43 ) and (tmr4 < 47) then goto start_ok '  bit of latitude might need more
goto bit_read
start_ok:
while bit_count < 100
tmr4=0   ' clear timer 
pir3.3=0  'clear timer overflow flag
while ( ! i_data) : wend 'wait here till input goes high 
t4con=6     ;  prescale 16 timer on
while ( i_data) : wend  ' wait here till input goes low
t4con=0   ' timer off
 if  pir3.3 then bits.0[bit_count]=1  ;  ontime > 340 uS  
else
  bits.0[bit_count]=0 '  the ontime < 340 uS 
endif
 bit_count=bit_count+1
wend
       
 return

[Dave]

As far as the IDLE high or IDLE low state, looking at the signal with a scope, where is the bus signal level when NO data is being sent? I would imagine it to be high, as most single wire communications use a passive sourced current to stimulate the bus wire (usually a resistor). That way there can be more than 1 device listening as well as more than 1 device able to answer a request. This is done by pulling the line LOW thru an open collector transistor or N channel fet.