Code:
'Constants here
' RF_Init_Values[0] = $28 'Standby mode, 915-928 MHz, VTune by inductors, ENABLE R1/P1/S1
RF_Init_Values[0] = $68 'RECEIVE mode, 915-928 MHz, VTune by inductors, ENABLE R1/P1/S1
RF_Init_Values[1] = $8C 'FSK, max IF gain, Packet Mode
RF_Init_Values[2] = $03 '100KHz Freq Dev
RF_Init_Values[3] = $07 '25 KBps
RF_Init_Values[4] = $0C 'for OOK mode, not apliable
RF_Init_Values[5] = $0F '16Bytes FIFO,
RF_Init_Values[6] = $77 '915MHz R1 Reg
RF_Init_Values[7] = $64 '915MHz P1 Reg
RF_Init_Values[8] = $32 '915MHz S1 Reg
RF_Init_Values[9] = $74 '920MHz R2 Reg
RF_Init_Values[10] = $62 '920MHz P2 Reg
RF_Init_Values[11] = $32 '920MHz S2 Reg
RF_Init_Values[12] = $38 'config mode for OOK, not apliable
RF_Init_Values[13] = $08 'RCV:IRQ0=payload ready + IRQ1=CRC OK
'TX: IRQ1=TXdone
RF_Init_Values[14] = $35 'FIFO starts filling when SYNC detected,TXDONE goes hi when done,
'RSSI IRQ when is above level set, enable PLL lock
RF_Init_Values[15] = $00 'RSSI interupt level zero - minimum
RF_Init_Values[16] = $A3 'default filters config
RF_Init_Values[17] = $38 'default filters config
RF_Init_Values[18] = $30 'sync word ON, 24bits, 0 errors tolerance
RF_Init_Values[19] = $07 'reserved reg
RF_Init_Values[20] = $00 'RSII status read register, 0.5dB / bit
RF_Init_Values[21] = $00 'OOK config reg
RF_Init_Values[22] = $53 '"S" 1st byte of sync word
RF_Init_Values[23] = $43 '"C" 2nd byte of sync word
RF_Init_Values[24] = $53 '"S" 3rd byte of sync word - my initials!
RF_Init_Values[25] = $00 '
RF_Init_Values[26] = $70 'Cutoff fcy = 200KHz, output power = 13dBm 0b000
RF_Init_Values[27] = $BC 'clk out by default 427KHz
RF_Init_Values[28] = $03 '3 bytes payload
RF_Init_Values[29] = $01 'initial MAC ADDRESS, only for test
RF_Init_Values[30] = $5E 'Fix Packet Lenght, 3 bytes preamble, whitening ON, CRC ON, Node ADDR|0x00|0xFF filtering
RF_Init_Values[31] = $80 'FIFO autocreal enable if CRC fails, Write to FIFO in stby mode
'MRF initialization here
debug "@ MRF init", 10
MRFConfigSel=0 'Select the chip
'Going to try using shiftout before using hardware SPI
for i=0 to 31 'Sets up the index var for data
MRFaddr=(i << 1) 'Shifts address 1 bit to left, automatically gets start,write, and stop bits
SHIFTOUT SDO, SCLK, 1,[MRFaddr,RF_Init_Values(i)] 'send data to register
debug "Addr=",bin8 MRFaddr," Value=",hex2 RF_Init_Values[i],13
next i
MRFConfigSel=1 'Deselect the chip
'Try to read back some registers as a test to see if they were written correctly
MRFConfigSel=0 'Select the chip
for i = 0 to 7 'Sets up address to read
MRFaddr=((i << 1) | $40) 'Shifts left 1 bit, sets $40 bit, automatically gets start, READ, and stop bits
SHIFTOUT SDO, SCLK, 1,[MRFaddr] 'Address to read
SHIFTIN SDI, SCLK, 0,[MRFSPIdata] 'Get data from reg
debug "MRF Config data: i=", dec1 i, " Register ", bin8 MRFaddr, " Data=", hex2 MRFSPIdata,13
next i
'Try sending something
debug "Try sending 3 bytes",13
XMIT_EN: i=0 'Register of interest
MRFaddr=(i<<1) 'Gets register address format
MRFConfigSel=0 'Select the chip
SHIFTOUT SDO, SCLK, 1,[MRFaddr,$88] 'send data, TRANSMIT, 915-928, Vtune by tank caps, Enable R1 P1 S1
MRFConfigSel=1 'Deselect the chip
XMIT: MRFDataSel=0
SHIFTOUT SDO, SCLK, 1,[$A1]
MRFDataSel=1
MRFDataSel=0
SHIFTOUT SDO, SCLK, 1,[$B1]
MRFDataSel=1
MRFDataSel=0
SHIFTOUT SDO, SCLK, 1,[$C1]
MRFDataSel=1
i=0 'Register of interest
MRFaddr=(i<<1) 'Gets register address format
MRFConfigSel=0 'Select the chip
SHIFTOUT SDO, SCLK, 1,[MRFaddr,$28] 'STANDBY, 915-928, Vtune by tank caps, Enable R1 P1 S1
MRFConfigSel=1 'Deselect the chip
' goto XMIT_EN 'Remark this line to be receive all the time, otherwise its xmitting all the time
RCV: i=0 'Register of interest
MRFaddr=(i<<1) 'Gets register address format
MRFConfigSel=0 'Select the chip
SHIFTOUT SDO, SCLK, 1,[MRFaddr,$68] 'send data, RECEIVE, 915-928, Vtune by tank caps, Enable R1 P1 S1
MRFConfigSel=1 'Deselect the chip
Wait4Pkt: If MRFIrq0=1 and MRFIrq1=1 then
MRFDataSel=0 'Select chip cuz we have a packet ready and CRC is good
SHIFTIN SDI, SCLK, 0,[data3] 'Get data from reg
MRFDataSel=1 'De-Select chip
MRFDataSel=0 'Select chip cuz we have a packet ready and CRC is good
SHIFTIN SDI, SCLK, 0,[data2] 'Get data from reg
MRFDataSel=1 'De-Select chip
MRFDataSel=0 'Select chip cuz we have a packet ready and CRC is good
SHIFTIN SDI, SCLK, 0,[data1] 'Get data from reg
MRFDataSel=1 'De-Select chip
debug "MRF payload: Data3=",hex2 data3," Data2=",hex2 data2," Data1=",hex2 data1,13
endif
goto Wait4Pkt
Re: MRF90XAM9A interfacing help
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