Multi CPU , design and interrupt control

[longpole001]

thanks for the insight in to your project,

my current project is getting large and although i am reviewing distribution of functions , some are more complex than i first thought , the code is likely to get to 256k over the next year of updates and development .

my current goal is to make the first revision work ok with min required fuctions and by about late march have the 2nd revision pcb , with the 2 cpu design / interface code started

The key is the interface and the code overhead ,

ill post a drawing of the planed interface , but basicly a spi with 2 software controlled pins , 1 out for interupt request, and 1 for cpu chip enable for spi control per cpu, the interface software will setup a control code and data arrangement with so many bytes in a buffer swap arrangement.

a common memory access and higher subroutine access command structure on the master for the slave access is currently in my mind. with this common base the cpu count can be increased easly and allow for lot more code space as fuctions expand.

ill try and get the pre design done in the coming weeks


cheers

Sheldon

[Demon]

Sheldon,

If your project might grow that much, you might want to consider adding unused PICs on your network for future distributed processing.

It's easier to have a chip sit idle on a board than ask users to open a product and add an expansion board (even that could be something to consider).

Robert