PBP command execution time

[Demon]

I can't, I tried 8MHz but the software said it couldn't keep up and lowered the speed.


EDIT: So I tried another approach and lowered the OSC speed, but I get INVALID OSC DEFINE whenever I try DEFINE OSC 1 or 2.

PIC 18F44K22, PBP 2.60c, MPASM v5.49

asm
; __CONFIG    _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_ON_1H & _PRICLKEN_OFF_1H & _FCMEN_ON_1H & _IESO_OFF_1H
 __CONFIG    _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_OFF_1H & _PRICLKEN_OFF_1H & _FCMEN_ON_1H & _IESO_OFF_1H
 __CONFIG    _CONFIG2L, _PWRTEN_ON_2L & _BOREN_SBORDIS_2L & _BORV_285_2L
 __CONFIG    _CONFIG2H, _WDTEN_OFF_2H
 __CONFIG    _CONFIG3H, _CCP2MX_PORTC1_3H & _PBADEN_OFF_3H & _CCP3MX_PORTE0_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _P2BMX_PORTC0_3H & _MCLRE_EXTMCLR_3H
 __CONFIG    _CONFIG4L, _STVREN_OFF_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
endasm

DEFINE OSC 1
;DEFINE OSC 64

OSCCON  = %00110000              ' OSCILLATOR CONTROL REGISTER
;OSCCON  = %01110000              ' OSCILLATOR CONTROL REGISTER
' bit 7 IDLEN: Idle Enable bit
'     R/W       1 = Device enters Idle mode on SLEEP instruction
'               0 = Device enters Sleep mode on SLEEP instruction
' bit 6-4 IRCF<2:0>: Internal RC Oscillator Frequency Select bits(2)
'     R/W       111 = HFINTOSC – (16 MHz)
'               110 = HFINTOSC/2 – (8 MHz)
'               101 = HFINTOSC/4 – (4 MHz)
'               100 = HFINTOSC/8 – (2 MHz)
'               011 = HFINTOSC/16 – (1 MHz)(3)
'           If INTSRC = 0 and MFIOSEL = 0:
'               010 = HFINTOSC/32 – (500 kHz)
'               001 = HFINTOSC/64 – (250 kHz)
'               000 = LFINTOSC – (31.25 kHz)
'           If INTSRC = 1 and MFIOSEL = 0:
'               010 = HFINTOSC/32 – (500 kHz)
'               001 = HFINTOSC/64 – (250 kHz)
'               000 = HFINTOSC/512 – (31.25 kHz)
'           If INTSRC = 0 and MFIOSEL = 1:
'               010 = MFINTOSC – (500 kHz)
'               001 = MFINTOSC/2 – (250 kHz)
'               000 = LFINTOSC – (31.25 kHz)
'           If INTSRC = 1 and MFIOSEL = 1:
'               010 = MFINTOSC – (500 kHz)
'               001 = MFINTOSC/2 – (250 kHz)
'               000 = MFINTOSC/16 – (31.25 kHz)
' bit 3 OSTS: Oscillator Start-up Time-out Status bit
'       R       1 = Device is running from the clock defined by FOSC<3:0> of the CONFIG1H register
'               0 = Device is running from the internal oscillator (HFINTOSC, MFINTOSC or LFINTOSC)
' bit 2 HFIOFS: HFINTOSC Frequency Stable bit
'       R       1 = HFINTOSC frequency is stable
'               0 = HFINTOSC frequency is not stable
' bit 1-0 SCS<1:0>: System Clock Select bit
'       R/W     1x = Internal oscillator block
'               01 = Secondary (SOSC) oscillator
'               00 = Primary clock (determined by FOSC<3:0> in CONFIG1H).

OSCCON2 = %00000100              ' OSCILLATOR CONTROL REGISTER 2
' bit 7 PLLRDY: PLL Run Status bit
'     R         1 = System clock comes from 4xPLL
'               0 = System clock comes from an oscillator, other than 4xPLL
' bit 6 SOSCRUN: SOSC Run Status bit
'     R         1 = System clock comes from secondary SOSC
'               0 = System clock comes from an oscillator, other than SOSC
' bit 5 Unimplemented: Read as ‘0’.
' bit 4 MFIOSEL: MFINTOSC Select bit
'     R/W=0     1 = MFINTOSC is used in place of HFINTOSC frequencies of 500 kHz, 250 kHz and 31.25 kHz
'               0 = MFINTOSC is not used
' bit 3 SOSCGO(1): Secondary Oscillator Start Control bit
'     R/W=0     1 = Secondary oscillator is enabled.
'               0 = Secondary oscillator is shut off if no other sources are requesting it.
' bit 2 PRISD: Primary Oscillator Drive Circuit Shutdown bit
'     R/W=1     1 = Oscillator drive circuit on
'               0 = Oscillator drive circuit off (zero power)
' bit 1 MFIOFS: MFINTOSC Frequency Stable bit
'     R         1 = MFINTOSC is stable
'               0 = MFINTOSC is not stable
' bit 0 LFIOFS: LFINTOSC Frequency Stable bit
'     R         1 = LFINTOSC is stable
'               0 = LFINTOSC is not stable

OSCTUNE = %10000000              ' OSCILLATOR TUNING REGISTER
;OSCTUNE = %11000000              ' OSCILLATOR TUNING REGISTER
' bit 7 INTSRC: Internal Oscillator Low-Frequency Source Select bit
'     R/W       1 = 31.25 kHz device clock derived from the MFINTOSC or HFINTOSC source
'               0 = 31.25 kHz device clock derived directly from LFINTOSC internal oscillator
' bit 6 PLLEN: Frequency Multiplier 4xPLL for HFINTOSC Enable bit(1)
'     R/W       1 = PLL enabled
'               0 = PLL disabled
' bit 5-0 TUN<5:0>: Frequency Tuning bits – use to adjust MFINTOSC and HFINTOSC frequencies
'     R/W       011111 = Maximum frequency
'               011110 =
'               • • •
'               000001 =
'               000000 = Oscillator module (HFINTOSC and MFINTOSC) are running at the factory calibrated frequency.
'               111111 =
'               • • •
'               100000 = Minimum frequency