Unless I can't use a Saleae probe properly, each asm macro ran in 1uS (4uS for one pass). That's not bad considering the chunk of asm in there.
I think you're not using it properly. As far as I can see you have the sampling rate set to 4Mhz, so there's no way the logic analyzer is going to resolve anythning shorter than 1us. Increase the sampling rate and see if it makes any difference.

By the way, these chk:rp macro things, aren't those assembler macros, ie they check, at compile time, if there's a need to switch banks and only then actually inserts the code? Ie, chk:rp isn't runtime code, it's assembly time code.

/Henrik.