H1 guys ,
well further feedback from Microchip on the EMB of the 18f87k22 series , indicate that at 16bit which they do not state the the Fmax speed in the Datasheet , is that the device will run the EMB at 64mhz (16Mhz instruction rate internal)
Silicon C5 fixes the wait state Errata to allow for upto 3 wait states on the chips connected to it., however code running in the EMB would be slower than on the PIC as a result of the wait states
Microchip states that the expected chips would need if running at 0 wait states a total access time < 21ns ( electrical spec 167 ( address to data valid time in datasheet figure 31-7, table 31-11) ,including the glue logic
This can only be done by using the Sram 16bit ( most are 10ns ) , with glue logic at about ( 5ns max) , where the code would be loaded from serial Flash into Sram before running
this method on surface may allow for the expansion of available ram to the PIC as well , but i am waiting on confirmation of this and some other timing clarification on the above tables in the datasheet
The points highlighted in the thread indicate that the generated hex file would need be edited at the 128k code boundary , sub divided into 2 hex files manually, then loaded in to the PIC program area , then into external flash , then from external flash into the sram for use at startup .
It should be noted that Sram of speed and glue logic is not cheep , in fact its comparable to adding the same size PIC again
but it may be a way forward , more info still needed from microchip
regards
Sheldon
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