I probably should have been clearer when I said there's nothing special you have to do when writing your program.
There was talk of having to use ASM and split the program into multiple sections, manually enter addreses, etc.
To enable MPASM to override the device size so you can use external memory you need to add a __MAXROM statement to the device .INC file, like so:
Code:
__MAXROM 0x1FFFFF ; 2Mbyte
I don't use PBP much anymore, so I just did that with an old 18F6680 (64K) program I had and built a 1.2MByte program using PBP 2.47
As you've all mentioned, the trick here is what to do with it once you're done. You have to get part of the hex file into internal memory, and the rest into the external flash chip. If you somehow want to program the devices using an external programmer, there are tools you can use to split the hex file into the needed segments. I'd recommend the hexmate utility that you can get for free w/some of the Microchip tools.
Personally, I think you'd be better off using a bootloader program running in the internal flash and just let the device itself program everything.
some other comments...
also the CE for wait states on external memory bus has been fixed in C5 release of silicon
Thanks for that. I didn't realize it had been fixed.
re reading the datasheet , section 31-1 - note1 Fmax= 25Mhz in 8 bit External Memory mode - FOR VDD VALUES 1.8 TO 3V ,
so i would think that as long as VDD is higher than 3V then Fmax = 64Mhz
I think you're mis-reading that statement. There's a period in that sentence that you've deleted.
In Figure 31-1 the note reads:
Note 1: FMAX = 25 MHz in 8-Bit External Memory mode.
For VDD values, 1.8V to 3V, FMAX = (VDD - 1.72)/0.02 MHz.
That puts a limit of 25MHz on FMAX when using 8-bit external mode. Period.
If you look later in the datasheet at Figure 31-6 it shows an external 8-bit bus cycle. At cycles Q3 and Q4 it shows fetching a byte from each of the byte-wide chips in a single Q period. At 64MHz, each OSC Qn is 16ns! That would be one fast flash chip!
Unfortunately, the datasheet doesn't show a fetch using a 16-bit device. App note AN869B shows a 16-bit fetch, and the timing is a lot more reasonable since it uses Q3 and Q4 together to fetch a single 16-bit value. If you combine that with a wait state (Figure 12) then you'd have a bus cycle of ~120ns, which would match up with the speed of most flash IC's.
The thing is you would still only have roughly a single cycle (16ns) to latch the multiplexed address info. I doubt that the PIC IO pins would actually be able to keep up with this speed. 25MHz would give a single Q time of 40ns, and a bus cycle of ~160ns. You could probably run a bit faster than this, say perhaps 32 or 40MHz before the IO pins quit working properly, but as I said there's nothing in the datasheet to guarantee that.
This is all pretty advanced stuff. You'd have to decide if it's worth all the bother or not. Of course, porting 120K of existing PBP code to something else is a lot of work too!
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