Hi,
I thought HSERIN flushed the buffer first thing - apparently not.... Or are you just concerned that what you describe MIGHT happen if you DON'T clear the buffer before issuing a HSERIN?

A quick look in the datasheet for a 18F25K22 doesn't really say (or I missed it) if RCREG is writable so I can't really answer that with certainty but how it's "usually" done is to read it untill there's no more data available.

Code:
RC1IF VAR PIR1.5   ' Alias to USART receive interrupt flag

WHILE RC1IF
  Dummy = RCREG1
WEND
Or, since the FIFO is only two bytes deep, simply
Code:
Dummy = RCREG1
Dummy = RCREG1
/Henrik.