Ha! Clearly more of BOTH would be encouraged.......
I'm re-making the truth table with the conditionals. I've always been better at diagramming and such - I'm sure a pattern may arise.
Once I have the new 'map' I'll see what I can do.
As far as TableIn=PORTA & %00110011, The dirty little secret DT showed me may come in handy for the INPUTS as well as it has for the OUTPUTS.
The 'trick' is that the IO is sequential in the memory map, so, just set the base address:
SYMBOL IN_PORT_PIN=PORTA ' starting address
for x=0 to 4 'only 5 inputs for this chip
IN_PORT_PIN.0=[x]
next x

OR just use alias - but that does 'bloat' the code......