no this option is for INT/intOPTION_REG.6=0 ;Int on falling edge. Is it possible?
having
won't really work as there is only one rac_int ,you only need one isr for itINT_Handler RAC_INT, _ENCODERA, PBP, yes
INT_Handler RAC_INT, _ENCODERB, PBP, yes
your isr needs to
1 determine state of enca and encb
2 compare this state to the previous (old_state)
3 determine if the move is forward ,backwards or invalid (bounce) and inc or dec the counter as req
4 save the current state to "old_state"
5 clear the rac interrupt flag (the auto flag clear does not always work for rac int)
having pauses and lcd outputs in isr will lead to tears , make isr's as short as possible is best practice
after thought
add capacitors to ground across the enca/b pins (try 0.1 uf) to minimise contact bounce
Bookmarks