I believe I may have found an acceptable work-around for this. It turns out that _part_ of the problem was the way I was handling the display multiplexing. I was writing to the TRIS byte on the same port as the 1wire link. Now I'm reading the TRIS byte and bitmasking the write.
But the real solution was to run the OWIN/OWOUT _in_ the interrupt. That way the 1wire commands are sync'd to the interrupt and complete before the next interrupt. I had to add some flags to steer the main loop and to indicate when the data is valid and should be proccessed, but that's not a big deal.
Thanks,
-Denny




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