Thanks a lot, Robert. On checking your code I noticed that bits <1:0> of register OSCCON are cleared in your code whereas I had entered them as 10 to select the Internal Oscillator Block. I corrected them to 00 to select Primary Clock as determined by CONFIG1H [FOSC<3:0>]. Register OSCCON2 settings do not seem to play any role in enabling PLL.

Now my 18F26K22 is running at 64MHz!

Thanks to Dave Purola too. In his code again, the last two bits of OSCCON are cleared.

My revised code is given below.

DEFINE OSC 64 'Clock Speed: 64MHz

asm
__CONFIG _CONFIG1H, _FOSC_INTIO67_1H & _PLLCFG_ON_1H & _PRICLKEN_ON_1H & _FCMEN_ON_1H & _IESO_OFF_1H
__CONFIG _CONFIG2L, _PWRTEN_ON_2L & _BOREN_OFF_2L & _BORV_285_2L
__CONFIG _CONFIG2H, _WDTEN_NOSLP_2H & _WDTPS_512_2H
__CONFIG _CONFIG3H, _CCP2MX_PORTC1_3H & _PBADEN_OFF_3H & _CCP3MX_PORTB5_3H & _HFOFST_OFF_3H & _T3CMX_PORTB5_3H & _P2BMX_PORTC0_3H & _MCLRE_INTMCLR_3H
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
__CONFIG _CONFIG5L, _CP0_OFF_5L & _CP1_OFF_5L
__CONFIG _CONFIG5H, _CPB_OFF_5H & _CPD_OFF_5H
__CONFIG _CONFIG6L, _WRT0_OFF_6L & _WRT1_OFF_6L
__CONFIG _CONFIG6H, _WRTC_OFF_6H & _WRTB_OFF_6H & _WRTD_OFF_6H
__CONFIG _CONFIG7L, _EBTR0_OFF_7L & _EBTR1_OFF_7L
__CONFIG _CONFIG7H, _EBTRB_OFF_7H
ENDASM

OSCCON = %11110000 'Internal oscillator is set to 16MHz; Primary Clock is selected as system clock.
OSCTUNE = %11000000 'HFINTOSC selected; PLL enabled; Factory calibrated frequency

ADCON0.0 = 0 'Disable ADC
ANSELA = 0
ANSELB = 0
ANSELC = 0

CM1CON0.7 = 0 'Disable comparator1
CM2CON0.7 = 0 'Disable comparator2

'Port direction
TRISA = 0 'All are Outputs
TRISB = 0 'All are Outputs
TRISC = 0 'All are Outputs

START:

PortC.3 = 1 : pause 500
PortC.3 = 0 : pause 500

GOTO START

end


- Bala