PIC24 clear SPI slave FIFO

[The Master]

Hi,

I'm using a PIC24FJ64GA002 chip as an SPI slave with FIFO buffers enabled. It has CLK, MOSI, MISO and SS pins connected.

The datasheet says:
"A transmission will be aborted when the SSx pin goes high and may be retried at a later time. Each data word is held in SPIxTXB until all bits are transmitted to the receiver"

My code only writes to the transmit FIFO while SSx is asserted. If SSx goes high at any point I want the transmit FIFO to be cleared and my code will retry the send later. The question is, how do I clear the entire transmit FIFO and SPIxTXB?

[TommyLehmann]

Hi,

I have a similar problem. Have you already found a solution?


Best regards

Tommy Lehmann

[towlerg]

I'm confused, your using a PIC24 with PICBasic? How so?

George

[Demon]

He's not. That's why Offtopic.

Robert

[The Master]

Tommy: I never got a definitive answer. My circuits never worked properly and I can't say if it was due to the buffer not clearing or some other bug so in the end I switched to the UART module instead. I prefer SPI for it's use of a clock line but UART won due to it's asynchronous nature which simplified a lot of the code. It's a shame the asynchronous version of SPI doesn't work in my chips.

George: I always use MPASM for PIC10/12/16/18 and ASM30 for PIC24. This question was about the PIC itself though so the language doesn't really matter (and, as Robert said, is why it's posted in Off Topic)

[Demon]

Off on a tangent, can you give your impression of ASM30, the costs of using it (software/hardware)?

I remember branch register and that's it from college. It's been bugging me to get back in asm ever since I saw some asm in this forum.

Robert