Counting Timer0 and Timer1 overflows without any interrupt handler

[Darrel Taylor]

The simulator is Proteus VSM from Labcenter in the UK.
It's a bit pricey, but does an amazing job. Couldn't do my job without it.

And I just want to point out how I have RA3 and RA4 tied together in the above schematic.
It's a very important part of making the freq. counter work.

[Archangel]

Thanks Darrel,
I never could get my head around how to do that before, now I see tmr0 is a counter, tmr1 is the time base.

[HenrikOlsson]

And I just want to point out how I have RA3 and RA4 tied together in the above schematic.
It's a very important part of making the freq. counter work.

OK, I'll bite.... Are using RA3 to gate the signal for the T0CKI-pin, hence the seriesresistor on the input?

/Henrik.

[Darrel Taylor]

The two pins tied together (and the resistor) serve two purposes.

1. You're right Henrik, since Timer0 on 16F's can't be stopped and started like all the other timers, it's used to gate the incoming signal.

2. You can't directly read the value in Timer0's prescaler. So after counting pulses for the 1 sec. window, you have to provide additional pulses to the input until the value in TMR0 changes. The number of pulses you add tells you how many counts were already in the prescaler. This gives the low Byte of the final 32-bit value.

The result is made up of the Timer0 overflows (HighWord), the TMR0 value (HighByte of the LowWord) and the prescaler value (LowByte of the LowWord)

[dw_picbasic]

Hmmmmm.
I was thinking I was going to have to use a mosfet solid state relay at the input from the frequency source, so that I could pump Timer0 through the remaining clock cycles necessary to raise its flag again.
I can see how pulling the Timer0 input pin high will disable the incoming clock from the frequency source.
But I can't see how it could be used to pump the remaining cycles to get Timer0 to its next overflow since there is no way to dis-engage the frequency source signal. The remaining clocking and the frequency source would conflict with one another.

Additionally, I was wondering if there is another way of pumping Timer0 to overflow, by using an internal software loop rather than doing it through an external clocking pin? I was wondering if a routine of adding 1 to TIMRL register and testing for a TMR1IF flag might work just as well.


Unless I'm wrong that the intent is to pump Timer0 from an output pin from the PIC?

Thanks :-]

[HenrikOlsson]

Hi,
To enable the counter you TRISA.3=1 (pin is input). To gate the count signal OFF you set TRISA.3=0 (pin is output) and pull the pin low (or high for that matter. The resistor in series with the input will protect the DUT from the "shorted" input.

Pulse the RA3 output in a loop until TMR0 again overflows. The pulses will override the input signal, there will be no conflicts because of the series resistor. As long as the RA3 output is LOW the input signal isn't seen by TMR0, when RA3 is high the input signal can't pull it low due to the series resistor. It'll work.

/Henrik.

[dw_picbasic]

Oh...that is just tooooo coool!!! :-D
Love these toys!!!
Thanks Henrik!!