thanks guys , i have added addtional 0.1 caps to the VDD,VSS , the AVDD and AVSS are connected to the Vdd,VSS ,with 10 uf caps on the 3v3 line
wondering what setting you have for adcon1 & ADCON2 ,

i am currently finding that putting a large TAD value of 12 is getting me more consistant values ,
, but like to minimise the time per read as much as possible

found setting the 2.048 Vref was not giving a consistent reads and setting it to AVDD is
so i used
adcon1= $00
adcon2 = %10101110

and not used the defin ADC_clock , ADC_sampleus commands

i am still at a loss to find why the values are large differences between the 16f1947 and this chip , except 16f1947 is 10 bit ADC
any way as long as the reading are consistent ill move forward

cheers

sheldon