All about Occillators? Frequency/PLL?

[rsocor01]

ok that got me even more confused
4mhz with a pll of 1 = 48mhz??? seems backwards
i thought it would be something like pll splits the freq into divisions so a pll1 would be no split
but 2 would double the freq.

Ok, let me get you even more confused . This is probably the graphic that Dave was referring to. Follow the red arrows that I drew.



And this is from the datasheet,

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.