All about Occillators? Frequency/PLL?

[wdmagic]

ok that got me even more confused
4mhz with a pll of 1 = 48mhz??? seems backwards
i thought it would be something like pll splits the freq into divisions so a pll1 would be no split
but 2 would double the freq.

[mackrackit]

I is not about math but about how the register is selected. Take a look at the data sheet, it has a nice graphic.

[rsocor01]

ok that got me even more confused
4mhz with a pll of 1 = 48mhz??? seems backwards
i thought it would be something like pll splits the freq into divisions so a pll1 would be no split
but 2 would double the freq.

Ok, let me get you even more confused . This is probably the graphic that Dave was referring to. Follow the red arrows that I drew.



And this is from the datasheet,

2.2.4 PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase
Locked Loop (PLL) circuit. This is provided specifically
for USB applications with lower speed oscillators and
can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and
ECPIO Oscillator modes. It is designed to produce a
fixed 96 MHz reference clock from a fixed 4 MHz input.

[Charlie]

Think of a PLL as a sort of frequency multiplier. It is actually a free running oscillator that is synchronized to an source at a lower frequency. The high frequency oscillator output is divided by an integer value and compared to the low frequency reference and the difference in when they both cross zero (the phase) is used to move the higher frequency slightly higher or lower - hence the name Phase Locked Loop. Clear as mud?