Quote Originally Posted by Andy Wood View Post
Can you elaborate on "Clock Stretching" please?
I'll let Wikipedia explain that ...
http://en.wikipedia.org/wiki/I%C2%B2...hing_using_SCL

In PBP when using I2CREAD/I2CWRITE, the Master would use ... DEFINE I2C_HOLD 1 ... to respond properly to Clock Stretching.
In I2C Slave mode, the MSSP module can automatically hold the SCL line low after each byte, which gives your program time to respond.

Are other interrupts only an issue when using bit-banged SPI or are there still problems when using the (M)SSP module?
Interrupts can only be a problem on SPI Slaves, which you're not going to bit-bang anyhow.
The Master dictates when the Slave needs to send data.
If the Slave's off in an interrupt, it may not be ready to send anything when the Master cracks it's whip.

The MSSP will generate interrupts to help the Slave be ready, and on an 18F that can be a High Priority interrupt that interrupts any Low priority interrupts which may be running.
But on a 16F, you can't interrupt an interrupt.

SPI does not have "Clock Stretching".
Be ready to send ... or lose data.
Typically, the SPI Master will have to wait long enough to insure the Slave had time to prepare.

Yes, you can do things like having a separate line to indicate when the SPI Slave is ready.
But technically, that would no longer be called SPI.