Henrik,
Thank you once again for the assistance and suggestions.

After implementing what you showed me and lots of staring at the data sheets I was able to get my code to compile and run this afternoon. One problem though, is that I am still only seeing a 31.2kHz 50% duty cycle square wave on the output of my pic. I am not sure what I have done. The only deviation I made from your suggestions was that I had to use CCP1 instead of CCP2 due to the way my board is already wired. (I could possibly reconfigure)

Please take a look at the following and see if you can spot my error.

Thanks again.


Code:
' Charger Program for PIC18F2523 Microprocessor
'      written in PICBasic 3.0.7

' Battery: Test Program for hight speed PWM
' PC Board Assembly: MAI-xyzpdq
' PC Board: MAI-123456
' Schematic: MAI-xxxxxx
' Program: MAI-yyyyyy


@ ERRORLEVEL -306			'ignore "page boundary" errors during compiling
ver		VAR BYTE[4]
ARRAYWRITE ver,["1.00"]

'PIC18F2523 Configuration Registers (Assembler)

#CONFIG
    CONFIG OSC = INTIO67    	; Set oscillator configuration Internal Oscillator
    CONFIG FCMEN = OFF	     	; Fail-Safe Clock Monitor Enable bit
    CONFIG IESO = OFF	      	; Internal/External Oscillator Switchover bit
    CONFIG PWRT = OFF	      	; Power-up Timer Enable bit
    CONFIG BOREN = SBORDIS  	; Brown out detector enabled SBOREN disabled
    CONFIG BORV = 2 	       	; Brown-Out voltage set to 2.7
    CONFIG WDT = OFF	       	; Watchdog Timer Enable bit
    CONFIG WDTPS = 32768       	; Watchdog Timer Postscale Select bits
    CONFIG CCP2MX = PORTC   	; CCP2 input/output is multiplexed with RB3
    CONFIG PBADEN = ON	     	; PORTB<4:0> pins are configured as analog I/O on Reset
    CONFIG LPT1OSC = OFF	   	; (DEF) Timer1 configured for high power operation
    CONFIG MCLRE = ON	      	; MCLR pin enabled; RE3 input pin disabled
    CONFIG STVREN = ON	     	; Stack Full/Underflow Reset Enable bit (0=disabled)
    CONFIG LVP = ON		       	; Single-Supply ICSP™ Enable bit (On = enabled)
    CONFIG XINST = OFF      	; Instruction set extension disabled
    CONFIG DEBUG = OFF	      	; Background debugger disabled, RB6 and RB7 I/O pins
    CONFIG CP0 = OFF			; Block 0 is not code protected
    CONFIG CP1 = OFF			; Block 1 is not code protected
    CONFIG CP2 = OFF			; Block 2 is not code protected
    CONFIG CP3 = OFF			; Block 3 is not code protected
    CONFIG CPB = OFF			;(DEF) Boot block is not code protected
    CONFIG CPD = OFF			;(DEF) Data EE is not read protected
    CONFIG WRT0 = OFF			;(DEF) Table 0 is not write protected
    CONFIG WRT1 = OFF			;(DEF) Table 1 is not write protected
    CONFIG WRT2 = OFF			;(DEF) Table 2 is not write protected
    CONFIG WRT3 = OFF			;(DEF) Table 3 is not write protected
    CONFIG WRTC = OFF			;(DEF) Configuration is not write protected
    CONFIG WRTB = OFF			;(DEF) Boot table is not write protected
    CONFIG WRTD = OFF			;(DEF) Data EE is not write protected
    CONFIG EBTR0 = OFF	     	;(DEF) Table 0 is not read protected
    CONFIG EBTR1 = OFF	     	;(DEF) Table 1 is not read protected
    CONFIG EBTR2 = OFF	     	;(DEF) Table 2 is not read protected
    CONFIG EBTR3 = OFF	     	;(DEF) Table 3 is not read protected
    CONFIG EBTRB = OFF	     	;(DEF) Boot table is not read protected
#ENDCONFIG

'-----------------------------------------------------------------------------
'			SETTING UP OSCILLATOR AND PWM SETTINGS
'-----------------------------------------------------------------------------

OSCCON  = %11110010				'use internal oscillator, set to 8 MHz
OSCTUNE.6 = 1					'PLL Enabled : OSC will now run at 32MHz

PR2 = 63						'pwm = 125000Hz (highest pwm for 256 steps)

DUTY			VAR WORD		'SET UP A VARIABLE FOR DUTY CYCLE
DUTY = 127						'WE SHOULD STILL HAVE A RESOLUTION OF 256 STEPS: THIS SETS PWM TO 50%

CCP1CON.4 = DUTY.0				'10 BITS OF PWM VALUES ARE SPLIT BETWEEN TWO REGISTERS
CCP1CON.5 = DUTY.1				'CCP1CON.<4:5> HOLDS THE LOWER 2  BITS
CCPR1L = (DUTY >> 2)			'CCPR1L HOLDS THE HIGH 8 BITS (SIX IN OUR SPECIFIC CASE)

TRISC.2 = 0						'MAKES CCP1 (PORT C PIN 3) AN OUTPUT
T2CON = %00000100				'SETS TMR2 PRESCALE VALUE AND ENABLES TIMER 2

CCP1CON = %00001100				'CONFIGURES CCP1 MODULE AS PWM: SEE PG 139 SECTION 15 OF DATA SHEET