Hi,
I don't think it'll recognise PLLEN directly so in order to enable the PLL (when using the internal oscillator) you'd do OSCTUNE.6 = 1 (set bit 6 of OSCTUNE).

The compiler recognises all the names of all the registers but not the names of each individual bit in the registers. You can, however create an alias and use it:
Code:
PLLEN VAR OSCTUNE.6  ' Of course you could give it any name you like.
PLLEN = 1
Your OSCCON = %11100010 would result in 4MHz on the internal oscillator (it's controlled by bits 4 thru 6, which I've highlighted in red, in that register). Set those three bits to 111 to get 8MHz from the oscillator (resulting in 32MHz once the PLL is enabled).

At 32MHz system clock and PR2=63 (not 16) you'll get 125kHz and 8 full bits (256 "steps"). But you need to "split" those 8bits so that the two lowest significant bits of your dutycycle value ends up in CCPxCON bits 4 and 5 (if you're using the second PWM module) and the upper 6 bits ends up the lower 8 bits of CCPRxL.

So, the actual value to get 50% would be 127 or 128 but, using the CCP2 module, you do something like
Code:
Duty = 127
CCP2CON.4 = Duty.0
CCP2CON.5 = Duty.1
CCPR2L = (Duty >> 2)
/Henrik.