Hardware PWM (HPWM) Clairification on 18F45K22

[neondale]

The part that was most helpful is the fact that PBP3 now defines all of its config bits in a very organized fashion for the new devices:

#IF __PROCESSOR__ = "18F45K22"
#MSG "** STARTING FIRMWARE COMPILATION **"
#MSG "COMPILING FIRMWARE (" + __FILE__ + ")"
#msg "FOR MICROCHIP PIC PROCESSOR (" + __PROCESSOR__ + ")"
#IF __LONG__ = 1
#MSG "PICBASIC COMPILER IS USING LONG VARIABLES (PBPL)"
#ELSE
#MSG "PICBASIC COMPILER IS USING WORD VARIALBLES (PBPW)"
#ENDIF
#CONFIG
CONFIG FOSC = INTIO67 ; Internal oscillator block
CONFIG PLLCFG = OFF ; Oscillator used directly
CONFIG PRICLKEN = OFF ; Primary clock can be disabled by software
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor disabled
CONFIG IESO = OFF ; Oscillator Switchover mode disabled
CONFIG PWRTEN = ON ; Power up timer Enabled
CONFIG BOREN = SBORDIS ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
CONFIG BORV = 190 ; VBOR set to 1.90 V nominal
CONFIG WDTEN = ON ; WDT is always enabled. SWDTEN bit has no effect
CONFIG WDTPS = 32768 ; 1:32768
CONFIG CCP2MX = PORTC1 ; CCP2 input/output is multiplexed with RC1
CONFIG PBADEN = OFF ; PORTB<5:0> pins are configured as digital I/O on Reset
CONFIG CCP3MX = PORTE0 ; P3A/CCP3 input/output is mulitplexed with RE0
CONFIG HFOFST = ON ; HFINTOSC output and ready status are not delayed by the oscillator stable status
CONFIG T3CMX = PORTC0 ; T3CKI is on RC0
CONFIG P2BMX = PORTD2 ; P2B is on RD2
CONFIG MCLRE = EXTMCLR ; MCLR pin enabled, RE3 input pin disabled
CONFIG STVREN = ON ; Stack full/underflow will cause Reset
CONFIG LVP = OFF ; Single-Supply ICSP disabled
CONFIG XINST = OFF ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
CONFIG DEBUG = OFF ; Disabled
CONFIG CP0 = OFF ; Block 0 (000800-001FFFh) not code-protected
CONFIG CP1 = OFF ; Block 1 (002000-003FFFh) not code-protected
CONFIG CPB = OFF ; Boot block (000000-0007FFh) not code-protected
CONFIG CPD = OFF ; Data EEPROM not code-protected
CONFIG WRT0 = OFF ; Block 0 (000800-001FFFh) not write-protected
CONFIG WRT1 = OFF ; Block 1 (002000-003FFFh) not write-protected
CONFIG WRTC = OFF ; Configuration registers (300000-3000FFh) not write-protected
CONFIG WRTB = OFF ; Boot Block (000000-0007FFh) not write-protected
CONFIG WRTD = OFF ; Data EEPROM not write-protected
CONFIG EBTR0 = OFF ; Block 0 (000800-001FFFh) not protected from table reads executed in other blocks
CONFIG EBTR1 = OFF ; Block 1 (002000-003FFFh) not protected from table reads executed in other blocks
CONFIG EBTRB = OFF ; Boot Block (000000-0007FFh) not protected from table reads executed in other blocks
#ENDCONFIG
#ELSE
#ERROR "FIRMWARE NOT SUPPORTED FOR " + __PROCESSOR__
#ERROR "FIRMWARE REQUIRES AN 18F45K22 PIC PROCESSOR"
#ERROR "!!! FIRMWARE COMPILATION ABORTED !!! "
#ENDIF

This is the config coding i am using in my pic processor now. to set up all of the config bits and change the Mux'ing of the CCP Modules. The Code is also ver helpful because i program a lot of different devices and if i have the wrong device set when i go to compile it... The Editor will "remind" me to change the output device type to the correct PIC. Melabs has done a great job and creating more functionality in the newest versions of the compilers.

Thanks Melabs for Being Awesome!!!