I'm trying to make it idiot proof(trying to prevent 10k phone calls because people are to lazy to read instruction sheet) and I only want to sell one sku if at all possible. and I could make another data line. But I would like only three wires between modules vcc, ground, and data.

a and x are initialized to 0 two lines above don't know why I didn't include that. And you are correct on the if statement.

The way that it works:

All processors Idle till they receive a 0 on ign. Once the first processor in line goes to zero. It goes to serin. if serin times out. This processor is then assumed to be the master. module is incremented by one to send ID to next processor. It then sends a ground signal out of "out" to advanced the next processor into serin. The master then serouts 5 times (even though I want it to be one). Then goes to a pulse counting state on "out". The second processor receives its module number from serin. stores to eeprom then, increments "module" sends a ground pulse to next processor to get it ready for serin in. After that each slave after that does the same. after it sends serout to next processor. It sends a ground pulse back to previous processor to count. Then it listens on "out" for ground pulse and everytime it gets a ground pulse it just sends the pulse out of "ign" back to the master which then counts how many slaves have been generated. Everything in program works flawlessly except for the serin and serout. as for some reason serin times out and then a slave thinks it is the master also. Just need to know why this is. It is either setup timing, noise (doubt it) or possibly when in serin state it looses its pull up resistor state on B.0 (which is enabled)