Shiftout data needs to be sent on rising edge of clock

[HenrikOlsson]

Hi Jim,
You won't be dissapointed with your LOGIC!
It does sound like the PIC outputs are driving something capacitive. You mention a cable which obviously is capacitive to some extent. However, since the clock and data both are transmitted thru the same cable (I assume) one would think that the loading/delay on the clock would be equal to that on the data-line thus making no practical difference.

Please let us know how it works out.

/Henrik.

[JimAvanti]

Henrik,
I am happy with the Logic. At first when I opened the case I thought they forgot to package the device until I realized how small it is! Very nice device. I was only able to sample between 8MHz-12MHz for some reason, but for anayzing the SPI it was a nice clean signal. Being able to see the data sent/received in Hex was a nice bonus feature. The chip I am trying to control seems to be the problem rather than what I am sending. I am going to try looking at the hardware SPI on the PIC instead to see if it makes a difference.

Hi Jim,
You won't be dissapointed with your LOGIC!
It does sound like the PIC outputs are driving something capacitive. You mention a cable which obviously is capacitive to some extent. However, since the clock and data both are transmitted thru the same cable (I assume) one would think that the loading/delay on the clock would be equal to that on the data-line thus making no practical difference.

Please let us know how it works out.

/Henrik.