18F2431 Learning Curve

[rsocor01]

Include the line

DEFINE OSC xx

And set all the options to disable (watchdog, brown-out, etc) to start with.

Robert

[HenrikOlsson]

Hi,
Here are the CONFIGs I use for my 2431:

#CONFIG
    CONFIG OSC = HSPLL
    CONFIG FCMEN = ON
    CONFIG IESO = OFF
    CONFIG PWRTEN = ON
    CONFIG BOREN = ON
    CONFIG BORV = 42
    CONFIG WDTEN = OFF
    CONFIG WDPS = 512
    CONFIG WINEN = OFF
    CONFIG PWMPIN = OFF
    CONFIG LPOL = HIGH
    CONFIG HPOL = HIGH
    CONFIG T1OSCMX = OFF
    CONFIG MCLRE = ON
    CONFIG STVREN = ON
    CONFIG LVP = OFF
    CONFIG DEBUG = OFF
    CONFIG CP0 = ON
    CONFIG CP1 = ON
    CONFIG CP2 = ON
    CONFIG CP3 = ON
    CONFIG CPB = OFF
    CONFIG CPD = OFF
    CONFIG WRT0 = OFF
    CONFIG WRT1 = OFF
    CONFIG WRT2 = OFF
    CONFIG WRT3 = OFF
    CONFIG WRTC = OFF
    CONFIG WRTB = OFF
    CONFIG WRTD = OFF
    CONFIG EBTR0 = OFF
    CONFIG EBTR1 = OFF
    CONFIG EBTR2 = OFF
    CONFIG EBTR3 = OFF
    CONFIG EBTRB = OFF
#ENDCONFIG

If you're running on the internal oscillator then you need to change from HSPLL to IRCIO.

The oscillator section of the datasheet indicates that the internal oscillator defaults to 4Mhz but looking at the initialization condition of the OSCCON register it seems like bits 4,5,6 are all zero on power up - which would give you 31kHz. If you then have the clock DEFINED to 8MHz your 500ms PAUSE will actually be 322 seconds....

So, without actually testing this I'd try something like

DEFINE OSC 8
OSCCON = %01110010   ' Internal oscillator, 8MHz

/Henrik.

[Aussie Barry]

Thanks Henrik.

There is SO MUCH in the datasheet for this device!
Just when you think you have everything under control, something else raises its ugly head

I will try your configs and recommended changes over the next 24-48 hours and report back - hopefully with good news.

I went out this afternoon and bought a couple of crystals to play with - just in case. I now have 4, 8 and 20Mhz crystals to plug in, if and when required.

Cheers
Barry
VK2XBP

[Aussie Barry]

Hi Henrik,

I am pleased to advise that I now have a simple LCDOUT and LED Blink program operating as expected.
When I went through the '2431 datasheet regarding OSCON Register I selected OSCON = %0111110 which is somewhat different to what you suggested.
Both work but I am curious to know how, when and why bits 0-3 of the OSCON register should be used. Any comments?

My next stage of experimentation will be to get the serial LCD display working in the background using the HSEROUT statement. From there I will move onto ADCin to read a pot and follow up with the HPWM command.

Progress is slow but I am trying to understand "why" things are the way they are in conjunction with learning "how" to do things.

Cheers
Barry
VK2XBP

[mackrackit]

when and why bits 0-3 of the OSCON register should be used.

No different from any other chip, they are readable bits. Read if you want to know their state....

[Aussie Barry]

Oh dear....
I am really showing my ignorance

Thanks Dave.

[mackrackit]

Oh dear....
I am really showing my ignorance

Thanks Dave.

Not ignorance, just overwhelmed.
Do not be too hard on yourself.

[HenrikOlsson]

Hi Barry,
That's great news!

Bits 0 and 1 in the OSCCON register are the System Clock Select Bits. If you look at Figure 3-8 in the datasheet (I link it here just to be sure we're looking at the same revision) you'll see in the upper right hand corner that they, together with the low four bits on CONFIH1H and via the MUX selects which of the various clock sources to use to "drive" the device. When bit 1 of OSCON is set the internal oscillator is selected and bit 0 of OSCON does not matter. You'll see the other options in the overview of the OSCCON register in page 36.

Bit 2 of OSCON (IOFS) is set by the device when the frequency of the internal oscillator block has stabilized, there should, AFAIK be no need for you to write that bit.

Bit 3 of OSCON (OSTS) is set by the device when the start-up timer for the primary oscillator (external x-tal, resonator or RC) has timed out and the oscillator can be considered running and stable. This is also a "read-bit", there should AFAIK be no need for you write this bit.

So, I wonder, didn't my suggested OSCCON=%01110010 work? In your message you say that you've set OSCCON to %0111110 which is only seven bits. I'm not sure if it's the forum messing up the format or if there's a typo?

Finally, you're probably not going to like this but I'm pretty sure that ADCIN doesn't work with the ADC on 18F2431. I know it didn't before and I can't remember seeing any updates regarding that. So, you'll have to resort to manually "running it". I believe Bruce has covered that too in one or more of his excellent posts so its shouldn't be too hard to figure out.

/Henrik.

[Aussie Barry]

Thanks Henrik.

I have downloaded the datasheet from your link - I have been working off a preliminary datasheet dated 2003...
At least we are on the same page now

Thanks also for the detailed explanation on OSCCON bits.

Just to clarify - I did mention in my previous post that both OSCCON setups worked. Also, there was a typo in my previous post; my setup was OSCCON = %01111110 (I left out one of the "1's")

ADCIN doesn't work with the ADC on 18F2431

Oh, man.... What a bummer!
Looks like I have more research to do on running it manually. I will do some searches and see what I can find from Bruce's previous posts.
I am almost too scared to ask why it doesn't work but I am sure as hell it caused some major grief for people in the past.

Cheers
Barry
VK2XBP

[HenrikOlsson]

I am almost too scared to ask why it doesn't work but I am sure as hell it caused some major grief for people in the past.

The reason is that the ADC is a bit different, and a bit more complicated, than on other chips. On the 18F2431 there are two sample and hold circuits so it can sample two analog voltages at the exact same time (and then convert them one after the other). It can also be setup to run continously in various configurations and put the results into a 4 word FIFO, an interrupt can be generated at various "fill levels" of the FIFO.

/Henrik.