Thanks guys...I'm now approaching this in a slightly different way & getting reasonable results (I think!)
I'm using timer1 gate & comparator2
Here's the sequence....
Comparator2 goes high....raises a gate on timer1...timer1 starts counting
Comparator2 goes low ....gate drops ...timer1 stops counting
When gate drops a timer1gate interrupt gets flagged
A DT Interrupt traps this (T1GATE_INT) & my program jumps to an ISR
I spit out the contents of timer1 in the ISR serially to my PC.
clear timer1
rinse repeat.
It seems I can get trap upto 4khz audio frequency with nowhere near as many spurious readings as before (I'm still using a sig gen though)....above 4khz the counts start going a bit erratic.
here's the timer1 readings for 4000hz (16Mz Oscillator)...
495
495
495
495
494
495
495
495
494
495
495
495
494
495
495
495
494
495
495
495
494
494
495
(the gate is only trapping 'half a waveform period' so the counts are half what you'd expect when detecting 4khz)
Pretty steady (they should be 500...& I can't quite account for where the missing counts are going!)
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