Hank do the numbers below 900 seem to make sense? We should be able to predict the TMR output based on some simple math. You are running 4MIPS (16Mhz OSC). so that would be .25uS per instruction. If the timer is running from Fosc, a 1 K signal would have a count of 4000? 1/1000 = 1mS. 1mS/.25uS=4000. Assuming the ISR fires 1 time per cycle. Likewise we would expect a count of around 8000 for a 500Hz signal. But either you don't have it set up as I assume, or something is wrong that will require seeing more of your code.
BTW, using my assumptions, 82.4Hz is 48,543.
330Hz = 12,121
600Hz = 6666
650Hz = 6153
I can't decide if that looks linear, but it should.
Also try clearing the TMR1 high byte and low byte seperatly in the ISR. I don't think this should help, but it can't hurt




Bookmarks