CMCON = 7 'turn off analog comparators which kill digital on port A
TRISA =%00000000 'all porta as outputs
TrisB.4=0
TrisB.5=0 ' make portb4:5 outputs
CMCON = 7 'turn off analog comparators which kill digital on port A
TRISA =%00000000 'all porta as outputs
TrisB.4=0
TrisB.5=0 ' make portb4:5 outputs
Last edited by Archangel; - 6th May 2012 at 09:45.
If you do not believe in MAGIC, Consider how currency has value simply by printing it, and is then traded for real assets.
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thank you archangel.
i will test it and let you know the result.
In addition to Archangel. From what I know of Isis/Proteus whatever it is called) you
- don't need to add a voltage regulator but some power terminal and assign them to Vdd.
- unless you modify the config fuses, you'll need to tie MCLR to Vdd,
Steve
It's not a bug, it's a random feature.
There's no problem, only learning opportunities.
Hi Daydream,
I am not sure if your drawing is complete (showing all components) or just simplified and if it is complete then you are missing the filter / anti-oscilation capacitors at the output of the 7805. Typically, at least a 1 uf tantilum capacitor is necessary and it does not hurt to add a .1 uf and then some larger value (greater than 10 uf). If it helps, usually pin 4 (MCLR) is tied to +5v thru a 10k resistor as Mister_e pointed out. Best, Ed
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