How do you know which version of silicon you have?

Does PBP 3.04 code take into account these below errata issues?

This looks suspect as I am using 9 bit HSEROUT mode with parity etc.


17. Module: EUSART
When performing back-to-back transmission in
9-bit mode (TX9D bit in the TXSTA register is
set), an ongoing transmission’s timing can be
corrupted if the TX9D bit (for the next
transmission) is not written immediately following
the setting of TXIF. This is because any
write to the TXSTA register results in a reset of
the baud rate timer which will effect any ongoing
transmission.
Work around
Load TX9D just after TXIF is set, either by polling
TXIF or by writing TX9D at the beginning of the
Interrupt Service Routine, or only write to TX9D
when a transmission is not in progress
(TRMT = 1).
Date Codes that pertain to this issue:
All engineering and production devices.

18. Module: EUSART
When performing back-to-back transmission in 9-bit
mode (TX9D bit in the TXSTA register is set), the
second byte may be corrupted if it is written into
TXREG immediately after the TMRT bit is set.
Work around
Execute a software delay, at least one half the
transmission’s bit time, after TMRT is set and prior
to writing subsequent bytes into TXREG.
Date Codes that pertain to this issue:
All engineering and production devices.
4. Module: Enhanced Universal
Synchronous Receiver
Transmitter (EUSART)
One bit has been added to the BAUDCON register
and one bit has been renamed. The added bit is
RXDTP and is in the location, BAUDCON<5>. The
renamed bit is the TXCKP bit (BAUDCON<4>),
which had been named SCKP.
The TXCKP (BAUDCON<4>) and RXDTP
(BAUDCON<5>) bits enable the Asynchronous
mode TX and RX signals to be inverted (polarity
reversed). RXDTP has no effect on the
Synchronous mode DT signal.
Register 18-3, on page 204, will be changed as
shown on page 3.
Work around
None required.
Date Codes that pertain to this issue:
All engineering and production devices
:?