The one thing I can see would help is not to do the transmission inside the interrupt loop. Not sure how PBP implements the HSEROUT (you'll need to look at the ASM list for that), but most compilers will check the buffer empty condition, load the USART, and (many times) wait until the buffers empty again before exiting the routine.
The USART normally consists of two registers: TXREG and TSR. You load the TXREG with the information you want to send, if the TSR is empty then the TXREG is loaded into the TSR on the next Tcy; this is not an issue. But if the TSR is full (or currently sending data) then you must wait until it empties before the TXREG can load it and create the Buffer Empty condition. Because the USART is a serial device, you could potentially need to wait for 8-bits to be serially sent, before the TXREG is emptied. This could cause a bottleneck on the transactions.
In your case, since you are receiving and sending at 9600bps on one side, and receiving at 10400bps on another; you could potentially hold the 10400bps, while waiting for the TXREG to clear. To work around this, you can load the TXREG directly (if it's empty), and if not, wait for the next go-around until it empties. That way you eliminate the potential of holding the 10400bps reception waiting for the 9600bps transmission. Hopefully this is a bit more clear.
Some Pseudo code:
Code:Main_Loop: PIE1.RCIE = FALSE '(disable EUSART Receive Interrupt Enable bit) IF PIR1.TXIF = TRUE THEN '(if TX buffer empty) nextout = nextout % buffer_size HSEROUT buffer[nextout] nextout = nextout + 1 ENDIF SERIN.... (perform SERIN routine, with timeout - this is important) PIE1.RCIE = TRUE '(enable EUSART Receive Interrupt Enable bit) GOTO Main_LoopCode:Interrupt Service: nextin = nextin % buffer_size HSERIN buffer[nextin] nextin = nextin + 1
Bookmarks