serial data ideas please

[HenrikOlsson]

Hi,
Do you have to echo the char from within the ISR? Perhaps you could set a flag indicating that there is data to send and then do the sending a out_ptr handling in the main routine. That way you'll spend less time in the ISR. Changing:

bufchar = buffer[ptr_out]               'Read buffer location
HSEROUT [BufChar]                       'Send the character

to

HSEROUT [buffer[ptr_Out]]

Might also save a couple of cycles.

However, I think the main culprit is the saving/restoring of the system variables when entering and exiting the ISR (which DT-INTS does for you). You should be able to run the 18F2620 at 32Mhz by enabling the PLL as languer says.

Just thinking out loud.....

[retepsnikrep]

I think I'm stuck with enabling the 32mhz mode. PBPRO is aware but the pic is not running at 32mhz :?

[HenrikOlsson]

Hi,
Normally you need to enable the PLL by setting the correct CONFIG (which you now have set to INTIO67) but it seems as if, when using the internal oscillator, you enable it by setting PLLEN bit (OSCTUNE.6) - which apparently have done... So, right now I can't think of anything in particular but I'd take an extra read thru the Oscillator section of the datasheet and take a look if there indeed IS a CONFIG which seems reasonable for internal oscillator WITH PLL.

/Henrik.

[languer]

The one thing I can see would help is not to do the transmission inside the interrupt loop. Not sure how PBP implements the HSEROUT (you'll need to look at the ASM list for that), but most compilers will check the buffer empty condition, load the USART, and (many times) wait until the buffers empty again before exiting the routine.

The USART normally consists of two registers: TXREG and TSR. You load the TXREG with the information you want to send, if the TSR is empty then the TXREG is loaded into the TSR on the next Tcy; this is not an issue. But if the TSR is full (or currently sending data) then you must wait until it empties before the TXREG can load it and create the Buffer Empty condition. Because the USART is a serial device, you could potentially need to wait for 8-bits to be serially sent, before the TXREG is emptied. This could cause a bottleneck on the transactions.

In your case, since you are receiving and sending at 9600bps on one side, and receiving at 10400bps on another; you could potentially hold the 10400bps, while waiting for the TXREG to clear. To work around this, you can load the TXREG directly (if it's empty), and if not, wait for the next go-around until it empties. That way you eliminate the potential of holding the 10400bps reception waiting for the 9600bps transmission. Hopefully this is a bit more clear.

Some Pseudo code:

Main_Loop:
    PIE1.RCIE = FALSE '(disable EUSART Receive Interrupt Enable bit)
    IF PIR1.TXIF = TRUE THEN '(if TX buffer empty)
        nextout = nextout % buffer_size
        HSEROUT buffer[nextout]   
        nextout = nextout + 1
    ENDIF
    SERIN.... (perform SERIN routine, with timeout - this is important)
    PIE1.RCIE = TRUE '(enable EUSART Receive Interrupt Enable bit)
    GOTO Main_Loop

Interrupt Service:
    nextin = nextin % buffer_size
    HSERIN buffer[nextin]   
    nextin = nextin + 1

[retepsnikrep]

Thanks for that idea. I'll try it

I'm still concerned that the pic is not running at 32mhz yet? My config must be wrong somewhere :?

[spcw1234]

I run an 18F2620 at 32MHZ with the internal OSC. Here is my config.

OSCCON=(percent)01110000               ' SET TO 8 MHZ internal oscillator
OSCTUNE=(percent)11000000              ' TURN ON PLL X4 FREQ NOW 32MHZ

replace (percent) with %

[retepsnikrep]

Shawn

Can you post this part of you config as well please?

#CONFIG
 __CONFIG _CONFIG1H, _OSC_INTIO67_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
 __CONFIG _CONFIG2L, _PWRT_OFF_2L & _BOREN_OFF_2L
 __CONFIG _CONFIG2H, _WDT_OFF_2H
 __CONFIG _CONFIG3H, _PBADEN_OFF_3H & _LPT1OSC_OFF_3H & _MCLRE_OFF_3H
 __CONFIG _CONFIG4L, _STVREN_OFF_4L & _LVP_OFF_4L & _XINST_OFF_4L & _DEBUG_OFF_4L
#ENDCONFIG