Will Interrupts affect on chip eeprom writing?

[HenrikOlsson]

Didn't know which PIC you're using so I just picked a datasheet I had available.
Not sure but I think that the note about masking and not disabling the interrupts must apply specifically for when using ON INTERRUPT. Ie, they are telling us to clear the interrupt enable flags instead of inserting the DISABLE directive.

/Henrik.

[MOUNTAIN747]

Masked interrupts!

Art, Henrik,
If interrupts are enabled in INTCON Control Register with Global GIE, all individual interrupts are masked if the item/items of interest are cleared and not in use. let us say RBIE Port B interrupt-on-change, RBIE is set to 1, RBIE is now unmasked and ready for use.

If we look at the 18F25K22 as Henrik has used for an example, GIE=1 Enables all unmasked interrupts, PEIE=1 Peripheral Interrupt Enable bit, RBIE=1 unmasked the PortB interrupt-on-change interrupt, it is now ready for use. All other interrupts are masked and not in use. If we look at page 161 para 11.5 Timer0 Interrupt, “The interrupt can be masked by clearing the TMR0IE bit of the INTCON register.
At least that’s the way I understand it.
Wayne

[MOUNTAIN747]

Art, I would add one more thing,

@ BCF INTCON, GIE
Write EEPROM...................................
@ BSF INTCON, GIE

should do the trick if using interrupts durring a Write to EEPROM.
Wayne

[Art]

Art, I would add one more thing,

@ BCF INTCON, GIE
Write EEPROM...................................
@ BSF INTCON, GIE

should do the trick if using interrupts durring a Write to EEPROM.
Wayne

I tried this, and all appears ok so far

[Darrel Taylor]

With all the quotes from the manual and datasheet, I thought for sure someone would have seen ...

The following DEFINE turns interrupts off and then back on within a
WRITE command. Do not use this DEFINE if interrupts are not used in the
program.

DEFINE WRITE_INT 1

The difference being that it is built-in to the WRITE command.

Interrupts only need to be disabled during the "unlock" sequence written to EECON2 which takes 5 instructions.
@ 4Mhz, that's only 5uS, @ 20Mhz it's 1uS.

By wrapping the WRITE command with GIE=0 / GIE=1, you are disabling interrupts for the full time it takes to complete the WRITE to EEPROM.
@ any OSC, that's 4-6mS.

Many interrupts can be lost in that much time.

[sayzer]

Just for the note.

I also had same issue as Art.
DEFINE WRITE_INT 1 did not solve the issue, but GIE solved.

BTW; I am also using
@ INT_DISABLE RX_INT
before the write command and then enable it.
Only by itself it did not work, DEFINE WRITE_INT 1 also did not work.
Disabling GIE worked.

[Darrel Taylor]

Sayzer,

How long ago was your issue?
And was your issue with WRITE or WRITECODE?

WRITE_INT was introduced in PBP 2.50, but it was only for the WRITE command.
In 2.60, WRITE_INT was extended to the WRITECODE command.

I've done many interrupt programs as you can imagine.
WRITE_INT has always worked for me.

If you have code that demonstrates a problem with WRITE_INT, no less than 3 people will be involved in fixing it immediately.

EDIT: Using WRITE or WRITECODE inside a PBP type INT_Handler doesn't count.