Will Interrupts affect on chip eeprom writing?

[Art]

Hi Guys,
No more to say really.. that is the question

[HenrikOlsson]

Hi Art,
Here's a quote from the manual on the WRITE command:

If interrupts are used in a program, they must be turned off (masked, not DISABLEd) before executing a WRITE, and turned back on (if desired) after the write instruction is complete. An interrupt occurring during a WRITE may cause it to fail.

And here's a quote from the datasheet on the PIC18F25K22

To write an EEPROM data location, the address must first be written to the EEADR register and the data written to the EEDATA register. The sequence in Example 7-2 must be followed to initiate the write cycle.

The write will not begin if this sequence is not exactly followed (write 55h to EECON2, write 0AAh to EECON2, then set WR bit) for each byte. It is strongly recommended that interrupts be disabled during this

code segment.

So, I think the answer is Yes - Interrupts can interfere with writes to the EEPROM.

/Henrik.

[Art]

Thanks
The datasheet for 16F87X is not so clear for on chip eeprom,
but it does say you can write to program memory with interrupts enabled.

What does it mean to say "(masked, not DISABLEd)" ??

[HenrikOlsson]

Didn't know which PIC you're using so I just picked a datasheet I had available.
Not sure but I think that the note about masking and not disabling the interrupts must apply specifically for when using ON INTERRUPT. Ie, they are telling us to clear the interrupt enable flags instead of inserting the DISABLE directive.

/Henrik.

[MOUNTAIN747]

Masked interrupts!

Art, Henrik,
If interrupts are enabled in INTCON Control Register with Global GIE, all individual interrupts are masked if the item/items of interest are cleared and not in use. let us say RBIE Port B interrupt-on-change, RBIE is set to 1, RBIE is now unmasked and ready for use.

If we look at the 18F25K22 as Henrik has used for an example, GIE=1 Enables all unmasked interrupts, PEIE=1 Peripheral Interrupt Enable bit, RBIE=1 unmasked the PortB interrupt-on-change interrupt, it is now ready for use. All other interrupts are masked and not in use. If we look at page 161 para 11.5 Timer0 Interrupt, “The interrupt can be masked by clearing the TMR0IE bit of the INTCON register.
At least that’s the way I understand it.
Wayne

[MOUNTAIN747]

Art, I would add one more thing,

@ BCF INTCON, GIE
Write EEPROM...................................
@ BSF INTCON, GIE

should do the trick if using interrupts durring a Write to EEPROM.
Wayne