What Darrel said.

AND

In a post made March 13th:
You answered your own question in (1) from the Midrange manual:
(1) " If the PWM duty cycle value is longer than the PWM period, the CCPx pin will not be cleared. This allows a duty cycle of 100%".

Any dutycycle value above 796 will result in 100% dutycycle. In other words your SIN-output will be distorted/clipped.
You have several values larger than 796 (4*199 (which is what you have PR2 set to, remember we've been thru this)) in your lookuptable so you are "overdriving" the dutycycle register and "clipping" will occur.

/Henrik.