JTCullins, It sound pretty straight forward to me...
The LTC1864 conversion cycle begins with the rising edgeof CONV. After a period equal to t
CONV, the conversion isfi nished. If CONV is left high after this time, the LTC1864goes into sleep mode drawing only leakage current. On thefalling edge of CONV, the LTC1864 goes into sample modeand SDO is enabled. SCK synchronizes the data transferwith each bit being transmitted from SDO on the fallingSCK edge. The receiving system should capture the datafrom SDO on the rising edge of SCK. After completing thedata transfer, if further SCK clocks are applied with CONVlow, SDO will output zeros indefi nitely.


It does oparate differently from the LTC1298 but I don't see the problem.. Just take the CONV line high for a period of time then take it low, after which you shift in the data... It's just that easy.....