I have done this many times. It works as follows:

The Master has either a hardware TX or a software TX serial port connected to the HARDWARE RX serial ports of all the slaves.
The slaves have all their SOFTWARE TX serial ports connected together and to the (preferably) Hardware or software RX port of the master.
The line connecting the slave's TX ports to the Master's RX port is pulled up with a 2.2K resistor to Vcc.
The slaves have their address stored in EEPROM, which they read on every power up.


The Master sends address,length, data and checksum.

The Slaves run a RX interrupt on their HARDWARE serial port.
If they see their address they start receiving data until they get a timeout on the HSERIN command (this is all inside the ISR)
When they get a timeout, they check the command, length and checksum.
If all is OK, they send a response out of their SOFTWARE serial port in OPEN COLLECTOR mode. This response is sent inside the recieve ISR,
so it will happen quickly after the data is received.
The slave's response has the slave address,length, data and checksum

After the Master makes a request, it waits only 20 mSec for the slave's response. But the data will be there.

Using HSERIN in an interrupt-driven mode for receive on the slave means you will never miss a request.
The fact that the slaves are sending in an open-collector mode means you will never have bus contention.

You have to run the slave SEROUT2 command in INVERTED (and OPEN COLLECTOR) mode.


It all works perfectly.

Something you may have to watch out for - when you enable the USART on some chips, you automatically "steal" both PORTC.7 and PORTC.6 for
the HARDWARE serial port. So, if you are using a device in this "hybrid mode" (hardware for receive, software for send) and you are using
ports C.7 and C.6, you have to enable the USART, and as soon as you receive the data, you then must DISABLE the USART before you can
do a software send on PORTC.6. After you are done sending, then you simply re-enable the USART.