Hi,
Lets say you're operating at 4Mhz, that means the timer running used to generated the PWM ticks along at 1MHz, you want 25kHz PWM frequency. This means that there is 40 timer ticks per PWM period (with prescaler 1:1). Now, writing anything between 0 and 39 to CCPR1L will control the duty cycle from 0-100% in steps of 2.5%. Write 20 to CCPR1L and you'll get ~50% dutycycle.

The two lower bits comes from the fact that the output can be be shut off at any of the 4 internal " clock steps" making up one instruction cycle (basically where FOsc/4 comes from). This means that instead of 40 "duty cycle steps" you'll get 160 (0-159)

So if you want 50% dutycycle (a value of 80) you have the binary value %01010000 you load the two lower bits (00) into CCP1CON.4 & 5 and the 6 higher bits into CCP1RL but shifted down so they "line up" with the LSB of the CCP1RL register. What happens is that the value 20 (10100) ends up in CCPR1L.

If you're operating at 4Mhz and PWM'ing at 38kHz there's a PWM period of 26.3158 timer ticks (that's not possible so I'm guessing you're actually running at 38461Hz (26 ticks per period). The dutycycle will have a range of 0 to 103, a ~50% dutycycle will have the value 52 (%00110100) . Load CCP1CON.4 and 5 with 0 and load CCPR1L with 13.

Hope I got this right, if not I hope someone will correct me!
/Henrik.