Smooth LED fading via PWM

[HenrikOlsson]

Hi Hank,
Hmm, you might be right. It just seems that a PR2 of 64 would be more "even" since 64*4=256. On the other hand, 63 is 111111 in binary and if we stick the two lower counter bits to that we 11111111 which is 255 and then a dutycycle value of 255 "should" be 100%.

You are "splitting" the dutycycle value, putting the 6 high bits in CCPR1L and the two low bits in CCP1CON.5 and .4 right?

/Henrik.

[HankMcSpank]

Hi Hank,

You are "splitting" the dutycycle value, putting the 6 high bits in CCPR1L and the two low bits in CCP1CON.5 and .4 right?

Yes I am. Here's what I'm seeing...

PR2 = 62 ....... 253 is final value (giving 254 steps ....0-253 etc)
PR2 = 63 ....... 256 is final value (giving 257 steps)
PR2 = 64 ....... 260 is final value (giving 261 steps)

I'm rather surprised that there's no obvious HPWM setting which would give exactly 256 steps (0-255), but I guess for most, 255 is as near 256 so as not to worry so a setting of PR2=63 should suffice.