PICs interrupts - I don't clearly understand the DS's "vocabulary"

[rsocor01]

3.- "external" interrupts?
This would be INT0, INT1 etc

Henrik,

Thank you for clarifying these concepts for many of us. Now, isn't INT0 and INT1 internally available in the chips? Do you mean by "External" that you are feeding an external clock signal to INT0 and INT1?

Robert

[HenrikOlsson]

Hi,
Not exactly sure what you mean. I guess you can trip the INT0 interrupt "internally" simply by setting the interrupt flag so in that sense they are available internally. But what is meant by external is that the event causing the interrupt is being external to the PIC itself, ie an event on the physical pin. In the case if INT0 (which is usually on PortB.0) either a rising a falling edge depending on how it's setup.

/Henrik.

[flotulopex]

One more question please,

What does this mean?

Shall it mean, that in XT, HS and LP Oscillator modes, no level change (from 1 to 0) will ever be seen by the PIC?

[mister_e]

I would bet those pins are assign to those you connect the Crystal to... so they're no longer regular I/O... I'm I right copain d'outre-mer?

[flotulopex]

Even Crystals have sometimes opaque zones....

Et bien le bonjour aux amis du pays du sirop d'érable