Exactly, but they don't mention you can't share the CLK line with others on the bus (if you go with the NAND gate aproach) which means you need a second CLK line and the pin you gained by using the NAND gates is gone. So, if you have more than one SPI device on the same CLK (like that memory device) it seems to me that it would be best not to go with the NAND gate aproach.

/Henrik.