Tibbo Ethernet shield

[dhouston]

&%$@!@%*((&*%##)(!

Tibbo released the EM500/GA1000 firmware about 10 days back. They published pinout diagrams showing how the EM500 had to connect to the GA1000 and another showing how it had to connect to the flash memory chip. I emailed their tech people to see if there was any chance of using a different pin arrangement and was told, "the lines will need to exclusive and cannot be mixed".

I did the layout for the shield discussed here and for another far more complex PCB based on their published wiring diagrams.

Today, I discover that the previously immutable pinouts have changed, making my PCB layouts obsolete. Luckily, I got a new wheelchair this month which blew my toy budget for the next few weeks so I have not yet ordered the boards. And, I'll now have plenty of time to redo the layouts. Both have been complicated by the need for a transistor AND gate between some of the lines so it may take some time.

I'm glad that Lester thinks so highly of these incompetent boobs. I think they need all the few friends they can get.

[dhouston]

Worse yet I'm not at all certain what they are using to connect the CLK (GPIO6) and CS (GPIO7) lines (see C). Can anybody provide a clarifying schematic using standard symbols?

[HenrikOlsson]

Hi Dave,
Looks like two ordinary NAND gates to me. The one connected to GPIO6 acts as an inverter and then "NANDS" with GPIO7 forcing the module to RESET when (and only when) GPIO7 (CS\) is high and GPIO6 (CLK) is LOW.

At least that is how I read it.

/Henrik.

[dhouston]

Thanks, Henrik. I thought about the same but I'm not very strong on logic gates.

Isn't the GA1000 going to be reset on every clock pulse whenever CS\ is high?

[HenrikOlsson]

Hi Dave,
Yes it is. But if the CLK line only goes to the GA1000 then there's no reason for any pulses to be present on the CLK line when the module isn't selected and I suspect they are thinking you'll have a dedicated SPI clock between the EM500 and the GA1000...

If you need to share the CLK signal between peripherals then a dedicated I/O for the RST-line would be required, if it can't be omitted all together and reset thryu hardware only. (?)

Again, that's just my understanding of it, take it for what it is.

[dhouston]

They explain it in the text above the pictures.

[HenrikOlsson]

Exactly, but they don't mention you can't share the CLK line with others on the bus (if you go with the NAND gate aproach) which means you need a second CLK line and the pin you gained by using the NAND gates is gone. So, if you have more than one SPI device on the same CLK (like that memory device) it seems to me that it would be best not to go with the NAND gate aproach.

/Henrik.