The way I read the sheet, its not a delay thing. Seems like the A/D uses the SCL to clock the result out, starting some number of clocks after the start bit. So no matter what you do, on the 12th(maybe wrong number, working from memory here)clock, data is comming out. better be ready to catch it. When you "shiftout" the command, thst starts the clock counting. that gives you start bit, then 4 more clocks (i think) then data is comming on the something more clock.
I will need to re-read section 6 to try and wrap my head around it. Let me know if you need more info, I will read some more.




Bookmarks