Hi Bert,
The byte is transfered from the input shift register to the FIFO buffer once all its bits (including the stop bit) are received proplerly - this is also the instant at which the interrupt flag gets set.

RCREG then "gets" the byte from the FIFO buffer at the instant you actually read RCREG. If there's nothing in the FIFO you'll get nothing (0). Reading RCREG removes the oldest byte from the FIFO.

Is it only the very first byte after boot up that is wrong or is it the first byte of every packet?

/Henrik.

PS. I love my LOGIC as well, it's just perfect for stuff like this!