Low frequency audio level detector using PIC ADC?

[HankMcSpank]

[QUOTE=tony45;99536]

Actually I think my revised method below will be better....

(VCC is 5V, AC signal will sit on 2.5V, therefore positive half of cycle samples @10 bits will be between 512 & 1024, negative parts of the cycle will be between 0 & 512)

1. Setup a timer to interrupt at a rate of 20khz

2. In the timer interrupt routine take an ADC sample into a variable

3. Compare the ADC sample to the last sample - if it's higher keep it, if it's smaller ignore it.

4. If the sample reads below 512 (half VCC - the signal's zero cross), then the highest sample from step 3 is signal 'peak', now zero the variable ready for the next positive cycle (ie samples above 512)

5. Run a bit of maths to convert peak voltage sample to RMS (ie multipy peak sample by .707 using some FP workaround)


i agree

Tony, Bert - The problem with step 4, is that in the absence of an equal or higher sample arriving (or, as you're proposing, while below zero point) my running peak variable is decremented (remember this code is emulating an analogue peak detect circuit - in such a circuit, the diode only lets through voltage that is higher.....and in the absence of a higher voltage the didoe is reverse biased & the cap starts discharging via a resistor - my running peak variable content decrements in this case).

This will utlimately mean that during the negative portions of the cycle, the running peak I've stored will decrement a fair bit, before the next positive part of the cycle returns & sets the peak high again - this is essentially like half wave rectification vs full wave - the former gives much more ripple, ie half wave ripple....

http://www.m.case.btinternet.co.uk/a...e_Smoothed.gif

...so what I end up with is pseudo ripple (a variable decrementing then being topped up) This is why when the ADC reading goes below zero (ie below 128 on an 8 bit sample), I want to flip the negative cycle up - to be a positive cycle. This greatly reduces any decrementing (pseudo cap disharging)

This diagrams illustrate the end goal in analogue waveform terms...

http://www.eleinmec.com/figures/018_04.gif

The 0V (zero crossing point) in my case is 2.5V (an ADC reading of 128)...I want to flip the negative part of the wave up. It not only reduces ripple...but halfs the amount of time to detect peak etc, leading to less ripple (peak detect fluctuations)

http://images-mediawiki-sites.theful...3847055696.png

I realise 10 bits would be better, but just wanted to keep it all simple while I'm ironing out all the issues.

N8NTA - tks for the tip about measuring the main loop time, I'll do that.

Hank, I think something is wrong with the settings. The toggle rate seems to represent a word timing out. For instance timer1 is 16 bit, full count is 65535. 65535*.0000005 = 32.7675mSec. that sure looks like your toggle rate!

So I would guess TMR0 is not clearing on a match!

Wow Bert - that's a great spot! This from the datasheet...

"The Special Event Trigger output of the CCP occurs immediately upon a match between the TMR1H, TMR1L register pair and the CCPRxH, CCPRxL registerpair. The TMR1H, TMR1L register pair is not reset
until the next rising edge of the Timer1 clock."

As far as I can gather. other than to set the CCP register (to select pin toggle vs special event ADC triggering) ...there's nothing else to be done - not sure how this one can be tackled?!!