Ok hank, since you choose to swallow the red pill, here goes:

PR works opposite from the timer's. Timers ALWAYS count up and generate interrupt (if enabled) on overflow, So for a given count, we preload the timer to start somewhere other then zero. PR on the other hand, is a match for the timer. So if PR=200, the timer will start counting (from zero). When it gets to 200 (TMR = PR), timer is reset and starts again. If there is no PR postscaler, interrupt will be set.

So a higher PR will yeild less interrupts. I would like to take back my statement about a "clean" main. You can NEVER acheive that in the literial sense if using interrupts by definiation it will be interrupted. On the other hand, lets say the main is 7 instructions, you would never expect main toggle to be less then 1/7th of its uninterupted rate. Do you see why?

Make sense?

How did I know 7 insctructions? Its just math. you are running a 8 Mhz clock. that becomes 2MIPS. (2 million insctructions per second). 1 instruction takes .0000005 sec * 7 = .0000035 seconds. 1/.0000035 = ~285KHz. Ok really this is the proof, but go backwards to get the number of instructions.