Okay, I've a little bit modified the Bruce's program.
It runs well in ISIS Proteus with my defined duty cycles, and all of the 6 PWM outputs works.
But there is a little problem :
As you can see, U and W phases are working properly, but not the V phase (the low-side PWM is not inverted like the others).
Here's my modified code :
Thanks in advance for any advice.Code:DEFINE LOADER_USED 1 DEFINE OSC 20 ' At 20MHz, to figure a PWM frequency of 19.455kHz ' TPWM = time period of PWM frequency ' PTPER = 12-bit period register PTPERL and PTPERH ' PTMRPS = PWM time base prescaler ' ' (PTPER+1)*PTMRPS 257 ' TPWM = ---------------- = ------------ = 0.0000514 ' Fosc/4 5000000 ' ' Frequency = 1/TPWM = 1/0.0000514 = 19.455kHz ' ' PWM resolution (bits resolution for duty cycle) ' ' log(20MHz/19.455kHz) 3.01 ' Resolution = ------------------ = ----------- = 10 bits ' .301 .301 ' so we'll need a word sized var for Duty uduty VAR WORD vduty VAR WORD wduty VAR WORD PORTB = 0 ' clear port latch TRISB = %11000000 ' PWM0,1,2,3,4,5 outputs TRISC = 2 ' RC1 = FLTA input (ground RC1 to halt PWM) ' RC1 should be pulled high for normal PWM operation ' when fault A is enabled. ' PCPWM init DTCON = %00000101 ' ~500nS dead-time (for complementary outputs only) PTCON0 = %00000100 ' 1:1 postscale, Fosc/4 1:1 prescale, free running mode ' PTCON0 = %00000100 would give 19.45kHz/4 PTPERL = 0 ' PTPERH = 1 ' PTPER = $0100 or 256d for ~19.45kHz ' PWM4,5 independent, PWM0,1,2,3 complementary PWMCON0 = %01010100 ' PWM[5:0] outputs enabled PWMCON1 = 1 ' updates enabled, overrides sync w/timebase PTCON1 = %10000000 ' PWM time base is ON, counts up FLTCONFIG = %00000011 ' enable fault A, cycle-by-cycle mode 'Phases duty test uduty = 800 ' ~50% vduty = 500 wduty = 300 pwmlp: ' PWM update loop 'PWM U phase PDC0L = uduty.LowByte PDC0H = uduty.HighByte 'PWM V phase PDC1L = vduty.LowByte PDC1H = vduty.HighByte 'PWM W phase PDC2L = wduty.LowByte PDC2H = wduty.HighByte goto pwmlp





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