PWM resolution refers to the duty cycle. Not the PWM frequency. The value you load into PR2 sets the period for the frequency you want.

Say you want a 125kHz frequency. The period of 125kHz is 1/125,000 = 8uS. Now say you're using the 32MHz internal oscillator.

With a prescaler of 1 the timer will increment every 125nS or 1/8MHz.

With the timer incrementing every 125nS, it takes 64 instruction cycles before the timer is = PR2.

When it's = the value in PR2, the timer is automatically reset, and the PWM output pin is toggled high.

You can see this in Figure 24-3 in the data sheet.

The duty cycle is set by loading CCPR1L and CCP1CON bits 5 and 4. CCPR1L is an 8-bit register and the 2-bits in CCP1CON are the 2 least significant bits of the up to 10-bit duty cycle.

When the timer = the value in CCPR1L, and the lower 2-bits = the 2-bit value in CCP1CON bits 5 and 4, the PWM output pin is forced low.

Figure 24-4 and note 1 explain how the timer is concatenated to form a 10-bit counter used to compare the timer count to the 10-bit duty cycles registers.

The higher the frequency, the lower the resolution of the duty cycle, since there's less time in the period for more steps to adjust the duty cycle.

It looks confusing at first, but if you spend a few minutes reading the data sheet and have a calculator handy to plug-in the values shown in tables 24-5, 6 and 7, to see how they work out, it gets a lot clearer.