Originally Posted by
rocket_troy
I have a PIC18F14K50 and ...13K50 variants and I need to configure the Master Clear MCLRE off (ie. disabled). It's bit 7 in the Config3H register. What's the easiest way to do this and does anyone have any advice or links to provide me with clearer understanding of the formats or protocols of how to set these registers?
Hello Troy,
Here is a link to what I think is the best way to set your config bits. http://www.picbasic.co.uk/forum/cont...o-your-Program
Check out 3.b
This allows you to set them in your code like this:
Code:
asm
__CONFIG _CONFIG1L, _CPUDIV_NOCLKDIV_1L & _USBDIV_OFF_1L
__CONFIG _CONFIG1H, _FOSC_HS_1H & _PLLEN_OFF_1H & _PCLKEN_ON_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
__CONFIG _CONFIG2H, _WDTEN_ON_2H & _WDTPS_512_2H
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _BBSIZ_OFF_4L & _XINST_OFF_4L
endasm
You will need to first comment them out of the C:/PBP/18F14K50.inc file. Then you will need to figure out what they all are from the data sheet and the C:\Program Files\Microchip\MPASM Suite\P18F14K50.INC file, and see what your options are:
Here is just a listing of what you will see when you read the P18F14K50.INC file. Notice that mclear off is in config3h.
Code:
;----- CONFIG1L Options --------------------------------------------------
_CPUDIV_NOCLKDIV_1L EQU H'E7' ; No CPU System Clock divide
_CPUDIV_CLKDIV2_1L EQU H'EF' ; CPU System Clock divided by 2
_CPUDIV_CLKDIV3_1L EQU H'F7' ; CPU System Clock divided by 3
_CPUDIV_CLKDIV4_1L EQU H'FF' ; CPU System Clock divided by 4
_USBDIV_OFF_1L EQU H'DF' ; USB clock comes directly from the OSC1/OSC2 oscillator block; no divide
_USBDIV_ON_1L EQU H'FF' ; USB clock comes from the OSC1/OSC2 divided by 2
;----- CONFIG1H Options --------------------------------------------------
_FOSC_LP_1H EQU H'F0' ; LP oscillator
_FOSC_XT_1H EQU H'F1' ; XT oscillator
_FOSC_HS_1H EQU H'F2' ; HS oscillator
_FOSC_ERCCLKOUT_1H EQU H'F3' ; External RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTH_1H EQU H'F4' ; EC, CLKOUT function on OSC2 (high)
_FOSC_ECH_1H EQU H'F5' ; EC (high)
_FOSC_ERC_1H EQU H'F7' ; External RC oscillator
_FOSC_IRC_1H EQU H'F8' ; Internal RC oscillator
_FOSC_IRCCLKOUT_1H EQU H'F9' ; Internal RC oscillator, CLKOUT function on OSC2
_FOSC_ECCLKOUTM_1H EQU H'FA' ; EC, CLKOUT function on OSC2 (medium)
_FOSC_ECM_1H EQU H'FB' ; EC (medium)
_FOSC_ECCLKOUTL_1H EQU H'FC' ; EC, CLKOUT function on OSC2 (low)
_FOSC_ECL_1H EQU H'FD' ; EC (low)
_PLLEN_OFF_1H EQU H'EF' ; PLL is under software control
_PLLEN_ON_1H EQU H'FF' ; Oscillator multiplied by 4
_PCLKEN_OFF_1H EQU H'DF' ; Primary clock is under software control
_PCLKEN_ON_1H EQU H'FF' ; Primary clock enabled
_FCMEN_OFF_1H EQU H'BF' ; Fail-Safe Clock Monitor disabled
_FCMEN_ON_1H EQU H'FF' ; Fail-Safe Clock Monitor enabled
_IESO_OFF_1H EQU H'7F' ; Oscillator Switchover mode disabled
_IESO_ON_1H EQU H'FF' ; Oscillator Switchover mode enabled
;----- CONFIG2L Options --------------------------------------------------
_PWRTEN_ON_2L EQU H'FE' ; PWRT enabled
_PWRTEN_OFF_2L EQU H'FF' ; PWRT disabled
_BOREN_OFF_2L EQU H'F9' ; Brown-out Reset disabled in hardware and software
_BOREN_ON_2L EQU H'FB' ; Brown-out Reset enabled and controlled by software (SBOREN is enabled)
_BOREN_NOSLP_2L EQU H'FD' ; Brown-out Reset enabled in hardware only and disabled in Sleep mode (SBOREN is disabled)
_BOREN_SBORDIS_2L EQU H'FF' ; Brown-out Reset enabled in hardware only (SBOREN is disabled)
_BORV_30_2L EQU H'E7' ; VBOR set to 3.0 V nominal
_BORV_27_2L EQU H'EF' ; VBOR set to 2.7 V nominal
_BORV_22_2L EQU H'F7' ; VBOR set to 2.2 V nominal
_BORV_19_2L EQU H'FF' ; VBOR set to 1.9 V nominal
;----- CONFIG2H Options --------------------------------------------------
_WDTEN_OFF_2H EQU H'FE' ; WDT is controlled by SWDTEN bit of the WDTCON register
_WDTEN_ON_2H EQU H'FF' ; WDT is always enabled. SWDTEN bit has no effect.
_WDTPS_1_2H EQU H'E1' ; 1:1
_WDTPS_2_2H EQU H'E3' ; 1:2
_WDTPS_4_2H EQU H'E5' ; 1:4
_WDTPS_8_2H EQU H'E7' ; 1:8
_WDTPS_16_2H EQU H'E9' ; 1:16
_WDTPS_32_2H EQU H'EB' ; 1:32
_WDTPS_64_2H EQU H'ED' ; 1:64
_WDTPS_128_2H EQU H'EF' ; 1:128
_WDTPS_256_2H EQU H'F1' ; 1:256
_WDTPS_512_2H EQU H'F3' ; 1:512
_WDTPS_1024_2H EQU H'F5' ; 1:1024
_WDTPS_2048_2H EQU H'F7' ; 1:2048
_WDTPS_4096_2H EQU H'F9' ; 1:4096
_WDTPS_8192_2H EQU H'FB' ; 1:8192
_WDTPS_16384_2H EQU H'FD' ; 1:16384
_WDTPS_32768_2H EQU H'FF' ; 1:32768
;----- CONFIG3H Options --------------------------------------------------
_HFOFST_OFF_3H EQU H'F7' ; The system clock is held off until the HFINTOSC is stable.
_HFOFST_ON_3H EQU H'FF' ; HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.
_MCLRE_OFF_3H EQU H'7F' ; RA3 input pin enabled; MCLR disabled
_MCLRE_ON_3H EQU H'FF' ; MCLR pin enabled; RA3 input pin disabled
;----- CONFIG4L Options --------------------------------------------------
_STVREN_OFF_4L EQU H'FE' ; Stack full/underflow will not cause Reset
_STVREN_ON_4L EQU H'FF' ; Stack full/underflow will cause Reset
_LVP_OFF_4L EQU H'FB' ; Single-Supply ICSP disabled
_LVP_ON_4L EQU H'FF' ; Single-Supply ICSP enabled
_BBSIZ_OFF_4L EQU H'F7' ; 1kW boot block size
_BBSIZ_ON_4L EQU H'FF' ; 2kW boot block size
_XINST_OFF_4L EQU H'BF' ; Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
_XINST_ON_4L EQU H'FF' ; Instruction set extension and Indexed Addressing mode enabled
_DEBUG_ON_4L EQU H'7F' ; Background debugger enabled, RA0 and RA1 are dedicated to In-Circuit Debug
_DEBUG_OFF_4L EQU H'FF' ; Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins
At the bottom of the file you will see the Mclear off setting. Add this to config3h. But since config3h isn't currently in your configs, you would have to add a config3h line, like this:
Code:
asm
__CONFIG _CONFIG1L, _CPUDIV_NOCLKDIV_1L & _USBDIV_OFF_1L
__CONFIG _CONFIG1H, _FOSC_HS_1H & _PLLEN_OFF_1H & _PCLKEN_ON_1H & _FCMEN_OFF_1H & _IESO_OFF_1H
__CONFIG _CONFIG2H, _WDTEN_ON_2H & _WDTPS_512_2H
__CONFIG _CONFIG3H, _MCLRE_OFF_3H
__CONFIG _CONFIG4L, _STVREN_ON_4L & _LVP_OFF_4L & _BBSIZ_OFF_4L & _XINST_OFF_4L
endasm
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